AD9276 datasheet(39/48 Pages) AD

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AD9276

Rev. 0 | Page 39 of 48

SERIAL PORT INTERFACE (SPI)

The AD9276 serial port interface allows the user to configure

the signal chain for specific functions or operations through a

structured register space provided inside the chip. The SPI

offers the user added flexibility and customization, depending

on the application. Addresses are accessed via the serial port

and can be written to or read from via the port. Memory is

organized into bytes that can be further divided into fields, as

documented in the Memory Map section. Detailed operational

information can be found in the Analog Devices, Inc., AN-877

Application Note, Interfacing to High Speed ADCs via SPI.

Three pins define the serial port interface, or SPI: SCLK, SDIO,

and CSB (see Table 16). The SCLK (serial clock) pin is used to

synchronize the read and write data presented to the device. The

SDIO (serial data input/output) pin is a dual-purpose pin that

allows data to be sent to and read from the internal memory map

registers of the device. The CSB (chip select bar) pin is an active

low control that enables or disables the read and write cycles.

Table 16. Serial Port Pins

Function

SCLK

Serial clock. Serial shift clock input. SCLK is used to

synchronize serial interface reads and writes.

SDIO

Serial data input/output. Dual-purpose pin that

typically serves as an input or an output, depending

on the instruction sent and the relative position in

the timing frame.

CSB

Chip select bar (active low). This control gates the

read and write cycles.

The falling edge of CSB in conjunction with the rising edge of

SCLK determines the start of the framing sequence. During an

instruction phase, a 16-bit instruction is transmitted, followed

by one or more data bytes, which is determined by Bit Field W0

and Bit Field W1. An example of the serial timing and its defini-

tions can be found in Figure 76 and Table 17.

DON’T

CARE

DON’T

CARE

DON’T

CARE

DON’T

CARE

SDIO

SCLK

CSB

tDH

tHIGH

tCLK

tLOW

tDS

R/W

A12

A11

A10

Figure 76. Serial Timing Details

Table 17. Serial Timing Definitions

Parameter

Timing (ns min)

Description

tDS

Setup time between the data and the rising edge of SCLK

tDH

Hold time between the data and the rising edge of SCLK

tCLK

Period of the clock

Setup time between CSB and SCLK

Hold time between CSB and SCLK

tHIGH

Minimum period that SCLK should be in a logic high state

tLOW

Minimum period that SCLK should be in a logic low state

tEN_SDIO

Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling

edge (not shown in Figure 76)

tDIS_SDIO

Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising

edge (not shown in Figure 76)

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