AD9276 datasheet(33/48 Pages) AD

33 / 48 page

AD9276

Rev. 0 | Page 33 of 48

ADC

The AD9276 uses a pipelined ADC architecture. The quantized

output from each stage is combined into a 12-bit result in the

digital correction logic. The pipelined architecture permits the

first stage to operate on a new input sample and the remaining

stages to operate on preceding samples. Sampling occurs on the

rising edge of the clock.

The output staging block aligns the data, corrects errors, and

passes the data to the output buffers. The data is then serialized

and aligned to the frame and output clocks.

CLOCK INPUT CONSIDERATIONS

For optimum performance, the AD9276 sample clock inputs

(CLK+ and CLK−) should be clocked with a differential signal.

This signal is typically ac-coupled into the CLK+ and CLK− pins

via a transformer or capacitors. These pins are biased internally

and require no additional bias.

Figure 63 shows the preferred method for clocking the AD9276.

A low jitter clock source, such as the Valpey Fisher oscillator

VFAC3-BHL−50 MHz, is converted from single-ended to differ-

ential using an RF transformer. The back-to-back Schottky

diodes across the secondary transformer limit clock excursions

into the AD9276 to approximately 0.8 V p-p differential. This

helps to prevent the large voltage swings of the clock from

feeding through to other portions of the AD9276, and it

preserves the fast rise and fall times of the signal, which are

critical to low jitter performance.

0.1µF

SCHOTTKY

DIODES:

HSM2812

3.3V

50Ω 100Ω

CLK–

CLK+

ADC

MINI-CIRCUITS

ADT1-1WT, 1:1Z

XFMR

VFAC3

OUT

Figure 63. Transformer-Coupled Differential Clock

If a low jitter clock is available, another option is to ac-couple

a differential PECL signal to the sample clock input pins, as

shown in Figure 64. The AD951x family of clock drivers offers

excellent jitter performance.

100Ω

0.1µF

240Ω

AD951x FAMILY

50Ω*

CLK

*50Ω RESISTOR IS OPTIONAL.

PECL DRIVER

3.3V

OUT

VFAC3

CLK–

CLK+

ADC

Figure 64. Differential PECL Sample Clock

0.1µF

AD951x FAMILY

50Ω*

CLK

*50Ω RESISTOR IS OPTIONAL.

LVDS DRIVER

3.3V

OUT

VFAC3

100Ω

CLK–

CLK+

ADC

Figure 65. Differential LVDS Sample Clock

In some applications, it is acceptable to drive the sample clock

inputs with a single-ended CMOS signal. In such applications,

CLK+ should be driven directly from a CMOS gate, and the

CLK− pin should be bypassed to ground with a 0.1 μF capacitor

in parallel with a 39 kΩ resistor (see Figure 66). Although the

CLK+ input circuit supply is AVDD1 (1.8 V), this input is

designed to withstand input voltages of up to 3.3 V, making the

selection of the drive logic voltage very flexible.

0.1µF

39kΩ

CMOS DRIVER

50Ω*

OPTIONAL

100Ω

0.1µF

CLK

*50Ω RESISTOR IS OPTIONAL.

AD951x FAMILY

3.3V

OUT

VFAC3

CLK–

CLK+

ADC

Figure 66. Single-Ended 1.8 V CMOS Sample Clock

0.1µF

CMOS DRIVER

50Ω*

OPTIONAL

100Ω

0.1µF

CLK

*50Ω RESISTOR IS OPTIONAL.

AD951x FAMILY

3.3V

OUT

VFAC3

0.1µF

CLK–

CLK+

ADC

Figure 67. Single-Ended 3.3 V CMOS Sample Clock

Clock Duty Cycle Considerations

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals. As a result, these ADCs may

be sensitive to the clock duty cycle. Commonly, a 5% tolerance is

required on the clock duty cycle to maintain dynamic performance

characteristics. The AD9276 contains a duty cycle stabilizer (DCS)

that retimes the nonsampling edge, providing an internal clock

signal with a nominal 50% duty cycle. This allows a wide range

of clock input duty cycles without affecting the performance of

the AD9276. When the DCS is on, noise and distortion perfor-

mance are nearly flat for a wide range of duty cycles. However,

some applications may require the DCS function to be off. If so,

keep in mind that the dynamic range performance can be affected

when operated in this mode. See Table 18 for more details on

using this feature.

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