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MAX5557ESA Datasheet(PDF) 3 Page - Maxim Integrated Products

Part # MAX5557ESA
Description  Low-Cost Stereo Audio DACs
PDF  19 Pages
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX5557ESA Datasheet(HTML) 3 Page - Maxim Integrated Products

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Low-Cost Stereo Audio DACs
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +4.75V to +5.5V, GND = 0V, ROUT_ = 10kΩ, COUT_ = 10pF, 0dBFS sine-wave signal at 997Hz, fLRCLK (fS) = 48kHz, fMCLK =
12.288MHz, measurement bandwidth 10Hz to 20kHz, unless otherwise specified. TA = -40°C to +85°C, unless otherwise noted.
Outputs are unloaded, unless otherwise noted. Typical values at VDD = +5V, TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC CHARACTERISTICS
Interchannel Gain Mismatch
0.1
0.4
dB
Gain Error
-5
+5
%
Gain Drift
100
ppm/°C
ANALOG OUTPUTS
Full-Scale Output Voltage
VOUTR, VOUTL
3.25
3.5
3.75
VP-P
DC Quiescent Output Voltage
VQ
Input code = 0
2.4
V
Minimum Load Resistance
RL
3k
Ω
Maximum Load Capacitance
CL
100
pF
Power-Supply Rejection Ratio
PSRR
VRIPPLE = 100mVP-P, frequency = 1kHz
66
dB
POP AND CLICK SUPPRESSION
Mute Attenuation
100
dB
Power-Up Until Bias Established
Figure 14
360
ms
Valid Clock to Normal Operation
Soft-start ramp time, Figure 15 (Note 5)
20
ms
DIGITAL AUDIO INTERFACE (SCLK, SDATA, MCLK, LRCLK)
Input-Voltage High
VIH
2.0
V
Input-Voltage Low
VIL
0.8
V
Input Leakage Current
IIN
-10
+10
µA
Input Capacitance
8pF
TIMING CHARACTERISTICS
Input Sample Rate
fS
2
50
kHz
MCLK/LRCLK = 512
10
MCLK/LRCLK = 384
20
MCLK Pulse-Width Low
tMCLKL
MCLK/LRCLK = 256
20
ns
MCLK/LRCLK = 512
10
MCLK/LRCLK = 384
20
MCLK Pulse-Width High
tMCLKH
MCLK/LRCLK = 256
20
ns
EXTERNAL SCLK MODE
LRCLK Duty Cycle
(Note 6)
25
75
%
SCLK Pulse-Width Low
tSCLKL
20
ns
SCLK Pulse-Width High
tSCLKH
20
ns
SCLK Period
tSCLK
1 / (128
x fS)
ns
LRCLK Edge to SCLK Rising
tSLRS
20
ns
LRCLK Edge to SCLK Rising
tSLRH
20
ns
SDATA Valid to SCLK Rising
tSDS
20
ns
SCLK Rising to SDATA Hold Time
tSDH
20
ns



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