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MAX5557ESA Datasheet(PDF) 4 Page - Maxim Integrated Products |
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MAX5557ESA Datasheet(HTML) 4 Page - Maxim Integrated Products |
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4 / 19 page ![]() Low-Cost Stereo Audio DACs 4 ________________________________________________________________________________________ ELECTRICAL CHARACTERISTICS (continued) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS INTERNAL SCLK MODE LRCLK Duty Cycle (Note 7) 50 % Internal SCLK Period tISCLK (Note 8) 1 / fSCLK ns LRCLK Edge to Internal SCLK tISCLKR tISCLK / 2 ns SDATA Valid to Internal SCLK tISDS MCLK period = tMCLK tMCLK + 10 ns SDATA Valid to Internal SCLK tISDH MCLK period = tMCLK tMCLK ns (VDD = +4.75V to +5.5V, GND = 0V, ROUT_ = 10kΩ, COUT_ = 10pF, 0dBFS sine-wave signal at 997Hz, fLRCLK (fS) = 48kHz, fMCLK = 12.288MHz, measurement bandwidth 10Hz to 20kHz, unless otherwise specified. TA = -40°C to +85°C, unless otherwise noted. Outputs are unloaded, unless otherwise noted. Typical values at VDD = +5V, TA = +25°C.) (Note 1) Note 1: 100% production tested at TA = +85°C. Limits to -40°C are guaranteed by design. Note 2: 0.5 LSB of triangular PDF dither added to data. Note 3: Guaranteed by design, not production tested. Note 4: PSRR test block diagram shown in Figure 1 denotes the test setup used to measure PSRR. Note 5: Volume ramping interval starts from establishment of a valid MCLK to LRCLK ratio. Total time is proportional to the sample rate (fS). 20ms based on 48ksps operation. Note 6: In external SCLK mode, LRCLK duty cycles are not limited, provided all data formatting requirements are met. See Figures 4–7. Note 7: The LRCLK duty cycle must be 50% ±1/2 MCLK period in internal SCLK mode. Note 8: The SCLK/LRCLK ratio can be set to 32, 48, or 64, depending on the device and the MCLK/LRCLK ratio selected. See Figures 4–7. MCLK SDATA LRCLK SCLK GND VDD SPECTRUM ANALYZER LOUT, ROUT ZG AUDIO SIGNAL GENERATOR (100mVP-P AT 1kHz) DC POWER SUPPLY (5VDC) MAX5556–MAX5559 + Figure 1. PSRR Test Block Diagram |
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