R28 datasheet(294/473 Pages) RENESAS

294 / 473 page

R8C/28 Group, R8C/29 Group

16. Clock Synchronous Serial Interface

Rev.2.10

Sep 26, 2008

Page 275 of 441

REJ09B0279-0210

Figure 16.19

Example of Clock Synchronous Serial I/O with Chip Select Operation during Data

Transmission (4-Wire Bus Communication Mode)

TDRE bit in

SSSR register

TEND bit in

SSSR register

Data write to SSTDR register

Processing

by program

SSCK

SSO

• CPHS bit = 0 (data change at odd edges) and CPOS bit = 0 (“H” when clock stops)

SCS

(output)

SSCK

• CPHS bit = 1 (data change at even edges) and CPOS bit = 0 (“H” when clock stops)

CPHS, CPOS: Bits in SSMR register

1 frame

TDRE bit in

SSSR register

TEND bit in

SSSR register

Data write to SSTDR register

Processing

by program

1 frame

High-impedance

SCS

(output)

TXI interrupt request

is generated

SSO

1 frame

TXI interrupt request

is generated

TEI interrupt request is

generated

TEI interrupt request is

generated

TXI interrupt request

is generated

TXI interrupt request

is generated

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