R28 datasheet(317/473 Pages) RENESAS

317 / 473 page

R8C/28 Group, R8C/29 Group

16. Clock Synchronous Serial Interface

Rev.2.10

Sep 26, 2008

Page 298 of 441

REJ09B0279-0210

16.3.3.4

Slave Transmit Operation

In slave transmit mode, the slave device outputs the transmit data while the master device outputs the receive

clock and returns an acknowledge signal.

Figures 16.36 and 16.37 show the Operating Timing in Slave Transmit Mode (I2C bus Interface Mode).

The transmit procedure and operation in slave transmit mode are as follows.

(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set bits WAIT and MLS in the

ICMR register and bits CKS0 to CKS3 in the ICCR1 register (initial setting). Set bits TRS and MST in

the ICCR1 register to 0 and wait until the slave address matches in slave receive mode.

(2) When the slave address matches at the 1st frame after detecting the start condition, the slave device

outputs the level set by the ACKBT bit in the ICIER register to the SDA pin at the rise of the 9th clock

cycle. At this time, if the 8th bit of data (R/W) is 1, bits TRS and TDRE in the ICSR register are set to 1,

and the mode is switched to slave transmit mode automatically. Continuous transmission is enabled by

writing transmit data to the ICDRT register every time the TDRE bit is set to 1.

(3) When the TDRE bit in the ICDRT register is set to 1 after writing the last transmit data to the ICDRT

TEND bit is set to 1, set the TEND bit to 0.

(4) The SCL signal is released by setting the TRS bit to 0 and performing a dummy read of the ICDRR

(5) Set the TDRE bit to 0.

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