R28 datasheet(313/473 Pages) RENESAS

313 / 473 page

R8C/28 Group, R8C/29 Group

16. Clock Synchronous Serial Interface

Rev.2.10

Sep 26, 2008

Page 294 of 441

REJ09B0279-0210

Figure 16.32

Operating Timing in Master Transmit Mode (I2C bus Interface Mode) (1)

Figure 16.33

Operating Timing in Master Transmit Mode (I2C bus Interface Mode) (2)

SDA

(master output)

SCL

(master output)

SDA

(slave output)

TDRE bit in

ICSR register

TEND bit in

ICSR register

ICDRT register

ICDRS register

R/W

Slave address

Address + R/W

Processing

by program

(2) Instruction of

start condition

generation

(3) Data write to ICDRT

(4) Data write to ICDRT

(5) Data write to ICDRT

Data 2

Address + R/W

Data 1

SDA

(master output)

SCL

(master output)

SDA

(slave output)

TDRE bit in

ICSR register

TEND bit in

ICSR register

ICDRT register

ICDRS register

Data n

Processing

by program

(6) Generate stop condition and

set TEND bit to 0

(3) Data write to ICDRT

A/A

(7) Set to slave receive mode

Data n

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