R28 datasheet(312/473 Pages) RENESAS

312 / 473 page

R8C/28 Group, R8C/29 Group

16. Clock Synchronous Serial Interface

Rev.2.10

Sep 26, 2008

Page 293 of 441

REJ09B0279-0210

16.3.3.2

Master Transmit Operation

In master transmit mode, the master device outputs the transmit clock and data, and the slave device returns an

acknowledge signal.

Figures 16.32 and 16.33 show the Operating Timing in Master Transmit Mode (I2C bus Interface Mode).

The transmit procedure and operation in master transmit mode are as follows.

(1) Set the STOP bit in the ICSR register to 0 to reset it. Then set the ICE bit in the ICCR1 register to 1

(transfer operation enabled). Then set bits WAIT and MLS in the ICMR register and set bits CKS0 to

CKS3 in the ICCR1 register (initial setting).

(2) Read the BBSY bit in the ICCR2 register to confirm that the bus is free. Set bits TRS and MST in the

ICCR1 register to master transmit mode. The start condition is generated by writing 1 to the BBSY bit

and 0 to the SCP bit by the MOV instruction.

(3) After confirming that the TDRE bit in the ICSR register is set to 1 (data is transferred from registers

ICDRT to ICDRS), write transmit data to the ICDRT register (data in which a slave address and R/W

are indicated in the 1st byte). At this time, the TDRE bit is automatically set to 0, data is transferred

from registers ICDRT to ICDRS, and the TDRE bit is set to 1 again.

(4) When transmission of 1 byte of data is completed while the TDRE bit is set to 1, the TEND bit in the

ICSR register is set to 1 at the rise of the 9th transmit clock pulse. Read the ACKBR bit in the ICIER

the slave device is not acknowledged when the ACKBR bit is set to 1, generate the stop condition. The

stop condition is generated by the writing 0 to the BBSY bit and 0 to the SCP bit by the MOV

instruction. The SCL signal is held “L” until data is available and the stop condition is generated.

(5) Write the transmit data after the 2nd byte to the ICDRT register every time the TDRE bit is set to 1.

(6) When writing the number of bytes to be transmitted to the ICDRT register, wait until the TEND bit is

set to 1 while the TDRE bit is set to 1. Or wait for NACK (the NACKF bit in the ICSR register is set to

1) from the receive device while the ACKE bit in the ICIER register is set to 1 (when the receive

acknowledge bit is set to 1, transfer is halted). Then generate the stop condition before setting bits

TEND and NACKF to 0.

(7) When the STOP bit in the ICSR register is set to 1, return to slave receive mode.

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