R28 datasheet(314/473 Pages) RENESAS

314 / 473 page

R8C/28 Group, R8C/29 Group

16. Clock Synchronous Serial Interface

Rev.2.10

Sep 26, 2008

Page 295 of 441

REJ09B0279-0210

16.3.3.3

Master Receive Operation

In master receive mode, the master device outputs the receive clock, receives data from the slave device, and

returns an acknowledge signal.

Figures 16.34 and 16.35 show the Operating Timing in Master Receive Mode (I2C bus Interface Mode).

The receive procedure and operation in master receive mode are shown below.

(1) After setting the TEND bit in the ICSR register to 0, switch from master transmit mode to master

receive mode by setting the TRS bit in the ICCR1 register to 0. Also, set the TDRE bit in the ICSR

(2) When performing the dummy read of the ICDRR register and starting the receive operation, the receive

clock is output in synchronization with the internal clock and data is received. The master device

outputs the level set by the ACKBT bit in the ICIER register to the SDA pin at the rising edge of the 9th

clock cycle of the receive clock.

(3) The 1-frame data receive is completed and the RDRF bit in the ICSR register is set to 1 at the rise of the

9th clock cycle. At this time, when reading the ICDRR register, the received data can be read and the

RDRF bit is set to 0 simultaneously.

(4) Continuous receive operation is enabled by reading the ICDRR register every time the RDRF bit is set

to 1. If the 8th clock cycle falls after the ICDRR register is read by another process while the RDRF bit

is set to 1, the SCL signal is fixed “L” until the ICDRR register is read.

(5) If the next frame is the last receive frame and the RCVD bit in the ICCR1 register is set to 1 (disables

the next receive operation) before reading the ICDRR register, stop condition generation is enabled after

the next receive operation.

(6) When the RDRF bit is set to 1 at the rise of the 9th clock cycle of the receive clock, generate the stop

condition.

(7) When the STOP bit in the ICSR register is set to 1, read the ICDRR register and set the RCVD bit to 0

(maintain the following receive operation).

(8) Return to slave receive mode.

R28 Datasheet(PDF) 314 Page - Renesas Technology Corp