R28 datasheet(311/473 Pages) RENESAS

311 / 473 page

R8C/28 Group, R8C/29 Group

16. Clock Synchronous Serial Interface

Rev.2.10

Sep 26, 2008

Page 292 of 441

REJ09B0279-0210

16.3.3

I2C bus Interface Mode

16.3.3.1

I2C bus Format

Setting the FS bit in the SAR register to 0 enables communication in I2C bus format.

Figure 16.31 shows the I2C bus Format and Bus Timing. The 1st frame following the start condition consists of

8 bits.

Figure 16.31

I2C bus Format and Bus Timing

R/W

DATA

A/A

(a) I2C bus format (FS = 0)

Transfer bit count (n = 1 to 8)

Transfer frame count (m = from 1)

R/W

DATA

A/A

(b) I2C bus format (when start condition is retransmitted, FS = 0)

Upper: Transfer bit count (n1, n2 = 1 to 8)

Lower: Transfer frame count (m1, m2 = 1 or more)

SLA

A/A

R/W

DATA

SLA

SDA

SCL

SLA

R/W

DATA

1 to 7

(1) I2C bus format

(2) I2C bus timing

Explanation of symbols

: Start condition

The master device changes the SDA signal from “H” to “L” while the SCL signal is held “H”.

SLA

: Slave address

R/W

: Indicates the direction of data transmit/receive

Data is transmitted from the slave device to the master device when R/W value is 1 and from the master device to the slave device when

R/W value is 0.

: Acknowledge

The receive device sets the SDA signal to “L”.

DATA : Transmit / receive data

: Stop condition

The master device changes the SDA signal from “L” to “H” while the SCL signal is held “H”.

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