R28 datasheet(320/473 Pages) RENESAS

320 / 473 page

R8C/28 Group, R8C/29 Group

16. Clock Synchronous Serial Interface

Rev.2.10

Sep 26, 2008

Page 301 of 441

REJ09B0279-0210

16.3.3.5

Slave Receive Operation

In slave receive mode, the master device outputs the transmit clock and data, and the slave device returns an

acknowledge signal.

Figures 16.38 and 16.39 show the Operating Timing in Slave Receive Mode (I2C bus Interface Mode).

The receive procedure and operation in slave receive mode are as follows.

(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set bits WAIT and MLS in the

ICMR register and bits CKS0 to CKS3 in the ICCR1 register (initial setting). Set bits TRS and MST in

the ICCR1 register to 0 and wait until the slave address matches in slave receive mode.

(2) When the slave address matches at the 1st frame after detecting the start condition, the slave device

outputs the level set in the ACKBT bit in the ICIER register to the SDA pin at the rise of the 9th clock

cycle. Since the RDRF bit in the ICSR register is set to 1 simultaneously, perform the dummy-read (the

read data is unnecessary because it indicates the slave address and R/W).

(3) Read the ICDRR register every time the RDRF bit is set to 1. If the 8th clock cycle falls while the

RDRF bit is set to 1, the SCL signal is fixed “L” until the ICDRR register is read. The setting change of

the acknowledge signal returned to the master device before reading the ICDRR register takes affect

from the following transfer frame.

(4) Reading the last byte is performed by reading the ICDRR register in like manner.

R28 Datasheet(PDF) 320 Page - Renesas Technology Corp