R28 datasheet(322/473 Pages) RENESAS

Part #	R28

Description	RENESAS 16-BIT SINGLE-CHIP MCU R8C FAMILY / R8C/2x SERIES

PDF	473 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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322 / 473 page

R8C/28 Group, R8C/29 Group

16. Clock Synchronous Serial Interface

Rev.2.10

Sep 26, 2008

Page 303 of 441

REJ09B0279-0210

16.3.4

Clock Synchronous Serial Mode

16.3.4.1

Clock Synchronous Serial Format

Set the FS bit in the SAR register to 1 to use the clock synchronous serial format for communication.

Figure 16.40 shows the Transfer Format of Clock Synchronous Serial Format.

When the MST bit in the ICCR1 register is set to 1, the transfer clock is output from the SCL pin, and when the

MST bit is set to 0, the external clock is input.

The transfer data is output between successive falling edges of the SCL clock, and data is determined at the

rising edge of the SCL clock. MSB-first or LSB-first can be selected as the order of the data transfer by setting

the MLS bit in the ICMR register. The SDA output level can be changed by the SDAO bit in the ICCR2 register

during transfer standby.

Figure 16.40

Transfer Format of Clock Synchronous Serial Format

SCL

SDA

R28 Datasheet(PDF) 322 Page - Renesas Technology Corp