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R28 Datasheet(PDF) 325 Page - Renesas Technology Corp |
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R28 Datasheet(HTML) 325 Page - Renesas Technology Corp |
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325 / 473 page  R8C/28 Group, R8C/29 Group 16. Clock Synchronous Serial Interface Rev.2.10 Sep 26, 2008 Page 306 of 441 REJ09B0279-0210 16.3.5 Noise Canceller The states of pins SCL and SDA are routed through the noise canceller before being latched internally. Figure 16.43 shows a Block Diagram of Noise Canceller. The noise canceller consists of two cascaded latch and match detector circuits. When the SCL pin input signal (or SDA pin input signal) is sampled on f1 and two latch outputs match, the level is passed forward to the next circuit. When they do not match, the former value is retained. Figure 16.43 Block Diagram of Noise Canceller C DQ Latch C DQ Latch Match detection circuit SCL or SDA input signal Internal SCL or SDA signal f1 (sampling clock) Period of f1 f1 (sampling clock) |
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