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R28 Datasheet(PDF) 326 Page - Renesas Technology Corp

Part # R28
Description  RENESAS 16-BIT SINGLE-CHIP MCU R8C FAMILY / R8C/2x SERIES
PDF  473 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R28 Datasheet(HTML) 326 Page - Renesas Technology Corp

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R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
Rev.2.10
Sep 26, 2008
Page 307 of 441
REJ09B0279-0210
16.3.6
Bit Synchronization Circuit
When setting the I2C bus interface to master mode, the high-level period may become shorter in the following
two cases:
• If the SCL signal is driven L level by a slave device
• If the rise speed of the SCL signal is reduced by a load (load capacity or pull-up resistor) on the SCL line.
Therefore, the SCL signal is monitored and communication is synchronized bit by bit.
Figure 16.44 shows the Timing of Bit Synchronization Circuit and Table 16.8 lists the Time between Changing
SCL Signal from “L” Output to High-Impedance and Monitoring of SCL Signal.
Figure 16.44
Timing of Bit Synchronization Circuit
1Tcyc = 1/f1(s)
Table 16.8
Time between Changing SCL Signal from “L” Output to High-Impedance and
Monitoring of SCL Signal
ICCR1 Register
Time for Monitoring SCL
CKS3
CKS2
0
0
7.5Tcyc
1
19.5Tcyc
10
17.5Tcyc
1
41.5Tcyc
VIH
Reference clock of
SCL monitor timing
SCL
Internal SCL



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