R28 datasheet(332/473 Pages) RENESAS

332 / 473 page

R8C/28 Group, R8C/29 Group

17. Hardware LIN

Rev.2.10

Sep 26, 2008

Page 313 of 441

REJ09B0279-0210

17. Hardware LIN

The hardware LIN performs LIN communication in cooperation with timer RA and UART0.

17.1

Features

The hardware LIN has the features listed below.

Figure 17.1 shows a Block Diagram of Hardware LIN.

Master mode

• Generates Synch Break

• Detects bus collision

Slave mode

• Detects Synch Break

• Measures Synch Field

• Controls Synch Break and Synch Field signal inputs to UART0

• Detects bus collision

NOTE:

The WakeUp function is detected by INT1.

Figure 17.1

Block Diagram of Hardware LIN

Timer RA

UART0

Interrupt

control

circuit

Bus collision

detection

circuit

Synch Field

control

circuit

RXD0 input

control

circuit

RXD0 pin

TXD0 pin

LSTART bit

SBE bit

LINE bit

Timer RA

interrupt

TIOSEL = 0

Hardware LIN

TIOSEL = 1

RXD data

Timer RA

underflow signal

BCIE, SBIE,

and SFIE bits

UART0 transfer clock

UART0 TE bit

Timer RA output pulse

UART0 TXD data

MST bit

LINE, MST, SBE, LSTART, BCIE, SBIE, SFIE: Bits in LINCR register

TIOSEL: Bit in TRAIOC register

TE: Bit in U0C1 register

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