R28 datasheet(336/473 Pages) RENESAS

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R8C/28 Group, R8C/29 Group

17. Hardware LIN

Rev.2.10

Sep 26, 2008

Page 317 of 441

REJ09B0279-0210

17.4

Functional Description

17.4.1

Master Mode

Figure 17.4 shows typical operation of the hardware LIN when transmitting a header field in master mode.

Figures 17.5 and 17.6 show an Example of Header Field Transmission Flowchart.

When transmitting a header field, the hardware LIN operates as described below.

(1) When the TSTART bit in the TRACR register for timer RA is set by writing 1 in software, the hardware

LIN outputs “L” level from the TXD0 pin for the period that is set in registers TRAPRE and TRA for

timer RA.

(2) When timer RA underflows upon reaching the terminal count, the hardware LIN reverses the output of

the TXD0 pin and sets the SBDCT flag in the LINST register to 1. Furthermore, if the SBIE bit in the

LINCR register is set to 1, it generates a timer RA interrupt.

(3) The hardware LIN transmits 55h via UART0.

(4) The hardware LIN transmits an ID field via UART0 after it finishes sending 55h.

(5) The hardware LIN performs communication for a response field after it finishes sending the ID field.

Figure 17.4

Typical Operation when Sending a Header Field

TXD0 pin

Synch Break

SBDCT flag in the

LINST register

IR bit in the TRAIC

Synch Field

IDENTIFIER

(1)

(2)

(3)

(4)

(5)

Set by writing 1 to the

B1CLR bit in the LINST

Cleared to 0 upon

acceptance of interrupt

request or by a program

Shown above is the case where

LINE = 1, MST = 1, SBIE = 1

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