R28 datasheet(339/473 Pages) RENESAS

339 / 473 page

R8C/28 Group, R8C/29 Group

17. Hardware LIN

Rev.2.10

Sep 26, 2008

Page 320 of 441

REJ09B0279-0210

17.4.2

Slave Mode

Figure 17.7 shows typical operation of the hardware LIN when receiving a header field in slave mode. Figure

17.8 through Figure 17.10 show an Example of Header Field Transmission Flowchart.

When receiving a header field, the hardware LIN operates as described below.

(1) Synch Break detection is enabled by writing 1 to the LSTART bit in the LINCR register of the hardware

LIN.

(2) When “L” level is input for a duration equal to or greater than the period set in timer RA, the hardware

LIN detects it as Synch Break. At this time, the SBDCT flag in the LINST register is set to 1.

Furthermore, if the SBIE bit in the LINCR register is set to 1, the hardware LIN generates a timer RA

interrupt. Then it goes to Synch Field measurement.

(3) The hardware LIN receives a Synch Field (55h). At this time, it measures the period of the start bit and

bits 0 to 6 by using timer RA. In this case, it is possible to select whether to input the Synch Field signal

to RXD0 of UART0 by setting the SBE bit in the LINCR register accordingly.

(4) The hardware LIN sets the SFDCT flag in the LINST register to 1 when it finishes measuring the Synch

Field. Furthermore, if the SFIE bit in the LINCR register is set to 1, it generates a timer RA interrupt.

(5) After it finishes measuring the Synch Field, calculate a transfer rate from the count value of timer RA

and set to UART0 and registers TRAPRE and TRA of timer RA again. Then it receives an ID field via

UART0.

(6) The hardware LIN performs communication for a response field after it finishes receiving the ID field.

Figure 17.7

Typical Operation when Receiving a Header Field

RXD0 pin

Synch Break

RXD0 input for

UART0

RXDSF flag in the

LINCR register

Synch Field

IDENTIFIER

(2)

(3)

(5)

(6)

Shown above is the case where

LINE = 1, MST = 0, SBE = 1, SBIE = 1, SFIE = 1

(4)

(1)

SBDCT flag in the

LINST register

SFDCT flag in the

LINST register

IR bit in the TRAIC

Set by writing 1 to the

B0CLR bit in the LINST

Cleared to 0 when Synch

Field measurement

finishes

Measure this period

Set by writing 1 to

the B1CLR bit in

the LINST register

Cleared to 0 upon

acceptance of

interrupt request or

by a program

Set by writing 1 to

the LSTART bit in

the LINCR register

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