IR3522

Page 9

V3.01

SYSTEM THEORY OF OPERATION

PWM Control Method

The PWM block diagram of the xPHASE3

with trailing edge modulation is used to provide system control. A voltage type error amplifier with high-gain and

wide-bandwidth, located in the Control IC, is used for the voltage control loop. The feed-forward control is

performed by the phase ICs as a result of sensing the Input voltage (FET’s drain voltage). The PWM ramp slope

will change with the input voltage and automatically compensate for changes in the input voltage. The input voltage

can change due to variations in the silver box output voltage or due to the wire and PCB-trace voltage drop related

to changes in load current.

.

GND

VOUT1

VOSNS1+

DACIN

VREF1

VOUT1

LGND

IOUT

PHSIN

VOSNS1-

CSIN-

CSIN+

GATEL

EAIN

GATEH

SW

VIN

FB1

EAOUT1

CLKOUT

CLKIN

PHSOUT

PGND

VCCL

VCCH

DACIN

CLKIN

PHSOUT

CSIN+

GATEL

EAIN

GATEH

IOUT

PHSIN

SW

PGND

VCCL

VCCH

CSIN-

PHSIN

PHSOUT

VID6

VID6

VID6

VID6

VID6

VID6

VID6

VID6

VID6

VID6

GATE DRIVE

VOLTAGE

-

+

+

+

ENABLE

RAMP

DISCHARGE

CLAMP

VREF1_FAST

CLOCK GENERATOR

CURRENT

SENSE

AMPLIFIER

R

S

SHARE ADJUST

ERROR AMPLIFIER

RESET

DOMINANT

PWM

LATCH

ERROR

AMPLIFIER

COUT

IR3522 CONTROL IC

IR3506 PHASE IC

PWM

COMPARATOR

PWM

COMPARATOR

VC CL

-

+

+

+

RAMP

DISCHARGE

CLAMP

ENABLE

SHARE ADJUST

ERROR AMPLIFIER

RESET

DOMINANT

PWM

LATCH

CURRENT

SENSE

AMPLIFIER

R

S

IR3506 PHASE IC

REMOTE SENSE

AMPLIFIER

VC CL

C CS

R CS

C FB1

R CS

C BST

C BST

C CS

C CP11

R FB12

RF B11

3K

C LK

D

Q

+

-

R CP1

3K

CC P12

C LK

D

Q

+

-

Figure 3 - PWM Block Diagram

Frequency and Phase Timing Control

The system oscillator is located in the Control IC and is programmable from 250 kHz to 9 MHZ by an external

resistor. The control IC clock signal (CLKOUT) is connected to CLKIN of all the phase ICs. The phase timing of the

phase ICs is controlled by a daisy chain loop. The control IC phase clock output (PHSOUT) is connected to the

phase clock input (PHSIN) of the first phase IC, and PHSOUT of the first phase IC is connected to PHSIN of the

second phase IC, etc. The last phase IC (PHSOUT) is connected back to PHSIN of the control IC to complete the

loop. During power up, the control IC sends out clock signals from both CLKOUT and PHSOUT pins and detects

the feedback at PHSIN pin to determine the phase number and monitor any fault in the daisy chain loop. Figure 4

shows the phase timing for a four phase converter.