LM5119 datasheet(11/24 Pages) NSC

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Detailed Operating Description

The LM5119 high voltage switching regulator features all of

the functions necessary to implement an efficient dual chan-

nel buck regulator that operates over a very wide input voltage

range. The LM5119 may be configured as two independent

regulators or as a single high current regulator with two inter-

leaved channels. This easy to use regulator integrates high-

side and low-side MOSFET drivers capable of supplying peak

currents of 2.5 Amps (VCC = 8V). The regulator control

method is based on current mode control utilizing an emulat-

ed current ramp. Emulated peak current mode control pro-

vides inherent line feed-forward, cycle-by-cycle current

limiting and ease of loop compensation. The use of an emu-

lated control ramp reduces noise sensitivity of the pulse-width

modulation circuit, allowing reliable processing of the very

small duty cycles necessary in high input voltage applications.

The switching frequency is user programmable from 50kHz

to 750kHz. An oscillator/synchronization pin allows the oper-

ating frequency to be set by a single resistor or synchronized

to an external clock. An under-voltage lockout and channel2

enable pin allows either both regulators to be disabled or

channel2 to be disabled with full operation of channel1. Fault

protection features include current limiting, thermal shutdown

and remote shutdown capability. The under-voltage lockout

input enables both channels when the input voltage reaches

a user selected threshold and provides a very low quiescent

shutdown current when pulled low. The LLP32 package fea-

tures an exposed pad to aid in thermal dissipation.

High Voltage Start-Up Regulator

The LM5119 contains two internal high voltage bias regula-

tors, VCC1 and VCC2, that provide the bias supply for the

PWM controllers and gate drive for the MOSFETs of each

regulator channel. The input pin (VIN) can be connected di-

rectly to an input voltage source as high as 65 volts. The

outputs of the VCC regulators are set to 7.6V. When the input

voltage is below the VCC set-point level, the VCC output will

track the VIN with a small dropout voltage. If VCC1 is in an

under voltage condition, channel2 will be disabled. This in-

terdependence is necessary to prevent channel2 from run-

ning open loop in the single output interleaved mode when

the channel2 error amplifier is disabled (if either VCC is in UV,

both channels are disabled).

The outputs of the VCC regulators are current limited at 25mA

(minimum) output capability. Upon power-up, the regulators

source current into the capacitors connected to the VCC pins.

When the voltage at the VCC pins exceed 4.9V and the UVLO

pin is greater than 1.25V, both channels are enabled and a

soft-start sequence begins. Both channels remain enabled

until either VCC pin falls below 4.7V, the UVLO pin falls below

1.25V or the die temperature exceeds the thermal limit thresh-

old.

When operating at higher input voltages the bias power dis-

sipation within the controller can be excessive. An output

voltage derived bias supply can be applied to a VCC pins to

reduce the IC power dissipation. The VCCDIS input can be

used to disable the internal VCC regulators when external bi-

asing is supplied. If VCCDIS >1.25V, the internal VCC regu-

lators are disabled. The externally supplied bias should be

coupled to the VCC pins through a diode, preferably a Schot-

tky (low forward voltage). VCCDIS has a 500k

Ω internal pull-

down resistance to ground for normal operation with no

external bias. The internal pull-down resistance can be over-

ridden by pulling VCCDIS above 1.25V through a resistor

divider connected to an external bias supply.

The VCC regulator series pass transistor includes a diode

between VCC and VIN that should not be forward biased in

normal operation.

If the external bias winding can supply VCC greater than VIN,

an external blocking diode is required from the input power

supply to the VIN pin to prevent the external bias supply from

passing current to the input supply through the VCC pins. For

VOUT between 6V and 14.5V, VOUT can be connected di-

rectly to VCC through a diode. For VOUT < 6V, a bias winding

on the output inductor can be added as shown in Figure 2.

30124011

FIGURE 2. VCC Bias Supply with Additional Inductor

Winding

In high voltage applications extra care should be taken to en-

sure the VIN pin does not exceed the absolute maximum

voltage rating of 75V. During line or load transients, voltage

ringing on the VIN line that exceeds the Absolute Maximum

Rating can damage the IC. Both careful PC board layout and

the use of quality bypass capacitors located close to the VIN

and AGND pins are essential.

UVLO

The LM5119 contains a dual level under-voltage lockout (UV-

LO) circuit. When the UVLO pin is less than 0.4V, the LM5119

is in shutdown mode. The shutdown comparator provides

100mV of hysteresis to avoid chatter during transitions. When

the UVLO pin voltage is greater than 0.4V but less than 1.25V,

the controller is in standby mode. In the standby mode the

VCC bias regulators are active but the controller outputs are

disabled. This feature allows the UVLO pin to be used as a

remote enable/disable function. When the VCC outputs ex-

ceed their respective under-voltage thresholds (4.9V) and the

UVLO pin voltage is greater than 1.25V, the outputs are en-

abled and normal operation begins.

An external set-point voltage divider from the VIN to GND is

used to set the minimum VIN operating voltage of the regu-

lator. The divider must be designed such that the voltage at

the UVLO pin will be greater than 1.25V when the input volt-

age is in the desired operating range. UVLO hysteresis is

accomplished with an internal 20

μA current source that is

switched on or off into the impedance of the set-point divider.

When the UVLO pin voltage exceeds 1.25V threshold, the

current source is activated to quickly raise the voltage at the

UVLO pin. When the UVLO pin voltage falls below the 1.25V

threshold, the current source is turned off causing the voltage

at the UVLO pin to quickly fall. The UVLO pin should not be

left floating.

LM5119 Datasheet(PDF) 11 Page - National Semiconductor (TI)

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