LM5119 datasheet(13/24 Pages) NSC

13 / 24 page

The sample-and-hold DC level is derived from a measure-

ment of the recirculating current flowing through the current

sense resistor. The voltage across the sense resistor is sam-

pled and held just prior to the onset of the next conduction

interval of the buck switch. The current sensing and sample-

and-hold provide the DC level of the reconstructed current

signal. The positive slope inductor current ramp is emulated

by an external capacitor connected from RAMP pin to AGND

and a series resistor connected between SW and RAMP. The

ramp resistor should not be connected to VIN directly be-

cause the RAMP pin voltage rating could be exceeded under

high VIN conditions. The ramp created by the external resistor

and capacitor will have a slope proportional to the rising in-

ductor current plus some additional slope required for slope

compensation. Connecting the RAMP pin resistor to SW pro-

vides optimum slope compensation with a RAMP capacitor

slope that is proportional to VIN. This “adaptive slope com-

pensation” eliminates the requirement for additional slope

compensation circuitry with high output voltage set points and

frees the user from additional concerns in this area. The em-

ulated ramp signal is approximately linear and the ramp slope

is given by:

(2)

The factor of 10 in equation (2) corresponds to the internal

current sense amplifier gain of the LM5119. The K factor is a

constant which adds additional slope for robust pulse-width

modulation control at lower input voltages. In practice this

constant can be varied from 1 to 3. R

S is the external sense

resistor value.

The voltage on the ramp capacitor is given by:

(3)

(4)

The approximation is the first order term in a Taylor Series

expansion of the exponential and is valid since t

PERIOD is small

relative to the RAMP pin R-C time constant.

Multiplying (2) by t

PERIOD to convert the slope to a peak volt-

age, and then equating (2) with (4) allows us to solve for

RAMP:

(5)

Choose either C

RAMP or RRAMP and use (5) to calculate the

other component.

The difference between the average inductor current and the

DC value of the sampled inductor current can cause instability

for certain operating conditions. This instability is known as

sub-harmonic oscillation, which occurs when the inductor rip-

ple current does not return to its initial value by the start of

next switching cycle. Sub-harmonic oscillation is normally

characterized by alternating wide and narrow pulses at the

switch node. The ramp equation above contains the optimum

amount of slope compensation, however extra slope com-

pensation is easily added by selecting a lower value for

RAMP or CRAMP.

Current Limit

The LM5119 contains a current limit monitoring scheme to

protect the regulator from possible over-current conditions.

When set correctly, the emulated current signal is proportion-

al to the buck switch current with a scale factor determined by

the current limit sense resistor, R

S, and current sense ampli-

fier gain. The emulated signal is applied to the current limit

comparator. If the emulated ramp signal exceeds 1.2V, the

present cycle is terminated (cycle-by-cycle current limiting).

Shown in Figure 4 is the current limit comparator and a sim-

plified current measurement schematic. In applications with

small output inductance and high input voltage, the switch

current may overshoot due to the propagation delay of the

current limit comparator. If an overshoot should occur, the

sample-and-hold circuit will detect the excess recirculating

current before the buck switch is turned on again. If the sam-

ple-and-hold DC level exceeds the internal current limit

threshold, the buck switch will be disabled and skip pulses

until the current has decayed below the current limit threshold.

This approach prevents current runaway conditions due to

propagation delays or inductor saturation since the inductor

current is forced to decay to a controlled level following any

current overshoot.

30124013

FIGURE 4. Current Limit and Ramp Circuit

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