LM5119 datasheet(12/24 Pages) NSC

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Enable 2

The LM5119 contains an enable function allowing shutdown

control of channel2, independent of channel1. If the EN2 pin

is pulled below 2.0V, channel2 enters shutdown mode. If the

EN2 input is greater than 2.5V, channel2 returns to normal

operation. An internal 50k

Ω pull-up resistor on the EN2 pin

allows this pin to be left floating for normal operation. The EN2

input can be used in conjunction with the UVLO pin to se-

quence the two regulator channels. If EN2 is held low as the

UVLO pin increases to a voltage greater than the 1.25V UVLO

threshold, channel1 will begin operation while channel2 re-

mains off. Both channels become operational when the UV-

LO, EN2, VCC1, and VCC2 pins are above their respective

operating thresholds. Either channel of the LM5119 can also

be disabled independently by pulling the corresponding SS

pin to AGND.

Oscillator and Sync Capability

The LM5119 switching frequency is set by a single external

resistor connected between the RT pin and the AGND pin

T). The resistor should be located very close to the device

and connected directly to the pins of the IC (RT and AGND).

To set a desired switching frequency (f

SW) of each channel,

the resistor can be calculated from the following equation:

(1)

Where RT is in ohms and f

SW is in Hertz. The frequency fSW

is the output switching frequency of each channel. The inter-

nal oscillator runs at twice the switching frequency and an

internal frequency divider interleaves the two channels with

180° phase shift between PWM pulses at the HO pins.

The RT pin can be used to synchronize the internal oscillator

to an external clock. The internal oscillator can be synchro-

nized by AC coupling a positive edge into the RT pin. The

voltage at the RT pin is nominally 1.25V and the voltage at

the RT pin must exceed 4V to trip the internal synchronization

pulse detector. A 5V amplitude signal and 100pF coupling

capacitor are recommended. Synchronizing at greater than

twice the free-running frequency may result in abnormal be-

havior of the pulse width modulator. Also, note that the output

switching frequency of each channel will be one-half the ap-

plied synchronization frequency.

Error Amplifiers and PWM

Comparators

Each of the two internal high-gain error amplifiers generates

an error signal proportional to the difference between the reg-

ulated output voltage and an internal precision reference

(0.8V). The output of each error amplifier is connected to the

COMP pin allowing the user to provide loop compensation

components. Generally a Type II network is recommended.

This network creates a pole at 0Hz, a mid-band zero, and a

noise reducing high frequency pole. The PWM comparator

compares the emulated current sense signal from the RAMP

generator to the error amplifier output voltage at the COMP

pin. Only one error amplifier is required when configuring the

controller as a two channel, single output interleaved regula-

tor. For these applications, the channel1 error amplifier (FB1,

COMP1) is configured as the master error amplifier. The

channel2 error amplifier must be disabled by connecting the

FB2 pin to the VCC2 pin. When configured in this manner the

output of the channel2 error amplifier (COMP2) will be dis-

abled and have a high output impedance. To complete the

interleaved configuration the COMP1 and the COMP2 pins

should be connected together to facilitate PWM control of

channel2 and current sharing between channels.

Ramp Generator

The ramp signal used in the pulse width modulator for current

mode control is typically derived directly from the buck switch

current. This switch current corresponds to the positive slope

portion of the inductor current. Using this signal for the PWM

ramp simplifies the control loop transfer function to a single

pole response and provides inherent input voltage feed-for-

ward compensation. The disadvantage of using the buck

switch current signal for PWM control is the large leading

edge spike due to circuit parasitics that must be filtered or

blanked. Also, the current measurement may introduce sig-

nificant propagation delays. The filtering, blanking time and

propagation delay limit the minimum achievable pulse width.

In applications where the input voltage may be relatively large

in comparison to the output voltage, controlling small pulse

widths and duty cycles are necessary for regulation. The

LM5119 utilizes a unique ramp generator which does not ac-

tually measure the buck switch current but rather reconstructs

the signal. Representing or emulating the inductor current

provides a ramp signal to the PWM comparator that is free of

leading edge spikes and measurement or filtering delays. The

current reconstruction is comprised of two elements; a sam-

ple-and-hold DC level and the emulated inductor current ramp

as shown in Figure 3.

30124012

FIGURE 3. Composition of Current Sense Signal

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