LM27402 datasheet(18/32 Pages) NSC

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FIGURE 13. Control Loop Schematic Diagram

The powertrain consists of the filter inductor (L) with DCR

DCR), output capacitor (COUT) with ESR (effective series re-

sistance R

ESR), and effective load resistance (RO). The error

amplifier (EA) regulates the feedback pin (FB) to 0.6V. The

passive compensation components around the error amplifier

help maintain system stability. Type III compensation is

shown in Figure 13. The PWM modulator establishes the duty

cycle command by comparing the error amplifier output

(COMP) with an internally generated ramp set at the switching

frequency.

The modulator gain, powertrain and compensator transfer

functions must be taken into consideration when obtaining the

total open loop transfer function. The PWM modulator adds a

DC gain to the open loop transfer function. In a basic voltage

mode system, the PWM gain will vary with input voltage.

However the LM27402 internal voltage feed-forward circuitry

maintains a constant PWM gain of 7:

The powertrain transfer function includes the output inductor

with DCR, output capacitor with ESR, and load resistance.

The inductor and capacitor create two complex poles at a fre-

quency described by:

A left half plane zero is created by the output capacitor ESR

located at a frequency described by:

The complete powertrain transfer function is:

The bode plot of the above transfer function can be seen in

Figure 14.

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FIGURE 14. Powertrain Bode Plot

The complex poles (f

LC) created by the filter inductor and out-

put capacitor cause a 180° phase shift as seen in Figure 14.

The phase is boosted back up to -90° by virtue of the output

capacitor ESR zero. The phase shift caused by the complex

poles must be compensated to stabilize the loop response.

The compensation network shown around the error amplifier

in Figure 13 creates two poles, two zeros and a pole at the

origin. Placing these poles and zeros at the correct frequen-

cies will optimize the loop response. The compensator trans-

fer function is:

The pole located at the origin provides high DC gain to opti-

mize DC load regulation performance. The other two poles

and two zeros can be located accordingly to stabilize the volt-

age mode loop depending on the power stage complex poles

and damping characteristic Q. Figure 15 is an illustration of

what the error amplifier compensation transfer function will

look like.

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