ATA6613 datasheet(18/364 Pages) ATMEL

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9111G–AUTO–05/10

ATA6612/ATA6613

3.3.24

Watchdog

The watchdog anticipates a trigger signal from the microcontroller at the NTRIG (negative edge)

input within a time window of T

wd . The trigger signal must exceed a minimum t i me

trigmin > 200 ns. If a triggering signal is not received, a reset signal will be generated at output

NRES. After a watchdog reset the IC starts with the lead time. The timing basis of the watchdog

is provided by the internal oscillator. Its time period, T

osc, is adjustable via the external resistor

wd_osc (34 kΩ to 120 kΩ).

During Silent or Sleep Mode the watchdog is switched off to reduce current consumption.

The minimum time for the first watchdog pulse is required after the undervoltage reset at NRES

disappears. It is defined as lead time t

d. After wake up from Sleep or Silent Mode, the lead time

d starts with the negative edge of the RXD output.

3.3.24.1

Typical Timing Sequence with R

WD_OSC = 51 kΩ

The trigger signal T

wd is adjustable between 20 ms and 64 ms using the external resistor

WD_OSC.

For example, with an external resistor of R

WD_OSC = 51 kΩ ±1%, the typical parameters of the

watchdog are as follows:

osc = 0.405 × RWD_OSC – 0.0004 × (RWD_OSC)

2 (R

WD_OSC in kΩ; tosc in µs)

OSC = 19.6 µs due to 51 kΩ

d = 7895 × 19.6 µs = 155 ms

1 = 1053 × 19.6 µs = 20.6 ms

2 = 1105 × 19.6 µs = 21.6 ms

nres = constant = 4 ms

After ramping up the battery voltage, the 3.3V/5V regulator is switched on. The reset output

NRES stays low for the time t

reset (typically 4 ms), then it switches to high, and the watchdog

waits for the trigger sequence from the microcontroller. The lead time, t

d, follows the reset and is

d = 155 ms. In this time, the first watchdog pulse from the microcontroller is required. If the trig-

ger pulse NTRIG occurs during this time, the time t

1 starts immediately. If no trigger signal

occurs during the time t

d, a watchdog reset with tNRES = 4 ms will reset the microcontroller after

d = 155 ms. The times t1 and t2 have a fixed relationship between each other. A triggering signal

from the microcontroller is anticipated within the time frame of t

2 = 21.6 ms. To avoid false trig-

gering from glitches, the trigger pulse must be longer than t

TRIG,min > 200 ns. This slope serves to

restart the watchdog sequence. If the triggering signal fails in this open window t

2, the NRES

output will be drawn to ground. A triggering signal during the closed window t

1 immediately

switches NRES to low.

ATA6613 Datasheet(PDF) 18 Page - ATMEL Corporation

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