PCF8532 datasheet(17/49 Pages) NXP

17 / 49 page

PCF8532

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Product data sheet

Rev. 2 — 10 February 2011

17 of 49

NXP Semiconductors

PCF8532

Universal LCD driver for low multiplex rates

When display data is transmitted to the PCF8532 the received display bytes are stored in

the display RAM in accordance with the selected LCD drive mode. The data is stored as it

arrives and does not wait for the acknowledge cycle as with the commands. Depending on

the current multiplex drive mode, data is stored singularly, in pairs, triples, or quadruples.

To illustrate the filling order, an example of a 7-segment numeric display showing all drive

modes is given in Figure 12; the RAM filling organization depicted applies equally to other

LCD types.

The following applies to Figure 12:

• In static drive mode the eight transmitted data bits are placed in row 0 as one byte.

• In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into

row 0 and 1 as two successive 4-bit RAM words.

• In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as

three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is

not recommended to use this bit in a display because of the difficult addressing. This

last bit may, if necessary, be controlled by an additional transfer to this address but

care should be taken to avoid overwriting adjacent data because always full bytes are

transmitted.

• In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples

into row 0, 1, 2, and 3 as two successive 4-bit RAM words.

The display RAM bitmap shows the direct relationship between the display RAM addresses and

the segment outputs; and between the bits in a RAM word and the backplane outputs.

Fig 11. Display RAM bitmap

1234

155 156 157 158 159

display RAM addresses (columns)/segment outputs (S)

display RAM bits

(rows)/

backplane outputs

(BP)

001aah853

PCF8532 Datasheet(PDF) 17 Page - NXP Semiconductors