PCF8532 datasheet(21/49 Pages) NXP

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PCF8532

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Product data sheet

Rev. 2 — 10 February 2011

21 of 49

NXP Semiconductors

PCF8532

Universal LCD driver for low multiplex rates

7.16 Characteristics of the I2C-bus

The I2C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must

be connected to a positive supply via a pull-up resistor when connected to the output

stages of a device. Data transfer may be initiated only when the bus is not busy.

In Chip-On-Glass (COG) applications, where the track resistance between the SDA

output pin to the system SDA input line can be significant, the bus pull-up resistor and the

Indium Tin Oxide (ITO) track resistance may generate a voltage divider. As a

consequence it may be possible that the acknowledge cycle, generated by the LCD driver,

cannot be interpreted as logic 0 by the master. Therefore it is an advantage for COG

applications to have the acknowledge output separated from the data line. For that

reason, the SDA line of the PCF8532 is split into SDA and SDAACK.

In COG applications where the acknowledge cycle is required, it is necessary to minimize

the track resistance from the SDAACK pin to the system SDA line to guarantee a valid

LOW level.

By splitting the SDA line into SDA and SDAACK (having the SDAACK open circuit), the

device could be used in a mode that ignores the acknowledge cycle. Separating the

acknowledge output from the serial data line can avoid design efforts to generate a valid

acknowledge level. However, in that case the I2C-bus master has to be set up in such a

way that it ignores the acknowledge cycle.2

By connecting pin SDAACK to pin SDA the SDA line becomes fully I2C-bus compatible.

The following definition assumes SDA and SDAACK are connected and refers to the pair

as SDA.

7.16.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as a control signal. Bit transfer is shown in Figure 13.

7.16.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy.

A HIGH-to-LOW change of the data line, while the clock is HIGH is defined as the START

condition (S).

For further information, please consider the NXP application note: Ref. 1 “AN10170”.

Fig 13. Bit transfer

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

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