PCF8532 datasheet(4/49 Pages) NXP

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PCF8532

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Product data sheet

Rev. 2 — 10 February 2011

4 of 49

NXP Semiconductors

PCF8532

Universal LCD driver for low multiplex rates

6.2 Pin description

[1]

In most applications SDA and SDAACK can be tied together.

[2]

The substrate (rear side of the die) is wired to VSS but should not be electrically contacted.

Table 3.

Pin description

Symbol

Description

SDAACK

1 to 3[1]

I2C-bus acknowledge output

SDA

4 to 6[1]

I2C-bus serial data input

SCL

7 to 9

I2C-bus serial clock input

CLK

clock input/output

VDD

11 to 13

supply voltage

SYNC

cascade synchronization input/output

OSC

selection of internal or external clock

T1, T2 and T3

16, 17 and 18 to 20 dedicated testing pins; to be tied to VSS in

application mode

A0 and A1

21, 22

subaddress inputs

SA0

I2C-bus slave address input

VSS

24 to 26[2]

logic ground

VLCD

27 to 29

LCD supply voltage

BP2 and BP0

30, 31

LCD backplane outputs

S0 to S79

32 to 111

LCD segment outputs

BP0, BP2, BP1 and BP3 112 to 115

LCD backplane outputs

S80 to S159

116 to 195

LCD segment outputs

BP3 and BP1

196, 197

LCD backplane outputs

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