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LC6529F Datasheet(PDF) 16 Page - Sanyo Semicon Device

Part # LC6529F
Description  4-Bit Microcomputer for Small-Scale Control Applications
PDF  39 Pages
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Manufacturer  SANYO [Sanyo Semicon Device]
Direct Link  https://www.sanyo-av.com/us/
Logo SANYO - Sanyo Semicon Device

LC6529F Datasheet(HTML) 16 Page - Sanyo Semicon Device

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Electrical Characteristics at Ta = –40 to +85°C, VSS = 0 V, VDD = 3.0 to 6.0 V
Note: * The RC oscillator and external clock options require a Schmidt trigger configuration for OSC1.
Note: * fCFOSC is the allowable oscillator frequency.
No. 5117-16/39
LC6529N, LC6529F, LC6529L
Parameter
Symbol
Conditions
min
typ
max
Unit
Open-drain (OD) configuration for port: With output
IIH1
N-channel transistor off. (Includes transistor’s leak
5.0
Input high level current
current.) VIN = 13.5 V
µA
IIH2
PE: Using port E configuration, VIN = VDD
1.0
IIH3
OSC1: Using external clock option, VIN = VDD
1.0
Open-drain (OD) configuration for port: With output
IIL1
N-channel transistor off. (Includes transistor’s leak
–1.0
current.) VIN = VSS
µA
Pull-up (PU) resistor configuration for port:
IIL2
With output N-channel transistor off. (Includes
–220
–71.5
transistor’s leak current.) VIN = VSS
Input low level current
Pull-up (PU) resistor configuration for port C:
IIL3
With output N-channel transistor off. (Includes
–6.00
–2.17
mA
transistor’s leak current.) VIN = VSS
IIL4
PE: Using port E configuration, VIN = VSS
–1.0
IIL5
RES: VIN = VSS
–45
–10
µA
IIL6
OSC1: Using external clock option, VIN = VSS
–1.0
VOH1
Pull-up (PU) resistor configuration for port C:
VDD – 1.2
Output high level voltage
IOH = –300 µA, VDD = 4 to 6 V
V
VOH2
Pull-up (PU) resistor configuration for port C:
VDD – 0.5
IOH = –60 µA
VOL1
PA, PC, PD: IOL = 10 mA, VDD = 4 to 6 V
1.5
Output low level voltage
VOL2
PA, PC, PD: With IOL for each port less than or equal
0.4
V
to 1 mA, IOL = 1.8 mA
Hysteresis voltage
VHIS1
RES
0.1 VDD
V
VHIS2
OSC1*: Using RC oscillator or external clock option
0.1 VDD
Parameter
Symbol
Conditions
min
typ
max
Unit
[Current drain]
Ceramic oscillator
IDD OP1
VDD: Figure 2, 4 MHz, 200 to 4330 kHz,
1.6
4.0
1/1 frequency divider
mA
External clock
IDD OP2
Note: With output N-channel transistor off and
1.6
4.2
port level = VDD
IDD st1
VDD: With output N-channel transistor off and
0.05
10
Standby operation
port level = VDD, VDD = 6 V
µA
IDD st2
VDD: With output N-channel transistor off and
0.025
5
port level = VDD, VDD = 3 V
[Oscillator characteristics] (Ceramic oscillator)
Oscillator frequency
fCFOSC
OSC1, OSC2: Figure 2, fO = 4 MHz*
3840
4000
4160
kHz
Oscillator stabilization interval
tCFS
Figure 3, fO = 4 MHz
10
ms
[Pull-up resistors]
Pull-up (PU) resistor configuration for port A or D:
RPP1
With output N-channel transistor off and VIN = VSS,
30
70
130
I/O ports
VDD = 5 V
Pull-up (PU) resistor configuration for port C:
k
Ω
RPP2
With output N-channel transistor off and VIN = VSS,
1.0
2.3
3.9
VDD = 5 V
Reset port
Ru
RES: VIN = VSS, VDD = 5 V
200
500
725
External reset characteristic:
tRST
See
Reset time
Figure 5.
Pin capacitance
CP
f = 1 MHz, VIN = VSS for pins other than one
10
pF
being measured



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