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LTC5588-1

55881fb

APPLICATIONS INFORMATION

At each baseband pin, a 0.146V to 0.854V swing is de-

veloped corresponding to a DAC output current of 0mA

to 20mA. A 3dB lower gain can be achieved using R1A =

R1B = 49.9Ω; R2A = R2B = Open; R2C = 100Ω; R3A =

R3B = 51Ω; L1A = L1B = L2A = L2B = 180nH; C1A = C1B

= C3A = C3B = 68pF; C2 = 56pF.

LO Section

The internal LO chain consists of a quadrature phase

shifter followed by LO buffers. The LOM input can be

driven single ended with 50Ω input impedance, while the

LOP input should be terminated with 50Ω through a DC

blocking capacitor.

The LOP and LOM inputs can also be driven differentially

when an exceptionally low large-signal output noise floor

is required.

A simplified circuit schematic for the LOP and LOM inputs

is given in Figure 3. Table 2 lists LOM port input imped-

ance vs frequency at EN = High and PLOM = 0dBm. For EN

= Low and PLOM = 0dBm the input impedance is given in

Table 3. The LOM port input impedance is shown for EN

= High and Low at PLOM = 10dBm in Table 4 and Table 5,

respectively. The circuit schematic of the demo board is

shown in Figure 8. A 50Ω termination can be connected

to the LOP port (J1).

The LOM port (J2) can also be terminated with a 50Ω

while the LO power is applied to the LOP (J1) port. In that

case, the image rejection may be degraded. At 2.14GHz,

the large-signal noise figure is about 2dB better for dif-

ferential LO drive (using BD1631J50100A00) with a LO

power below 10dBm. The balun (U2) can be installed

by removing C5 and C6 (see Figure 8). Using Anaren

P/N B0310J50100A00 improves image, LO leakage and

large-signal noise performance at 240MHz and 450MHz.

For this particular balun, an external blocking capacitor

is required.

Figure 4 shows the return loss vs RF frequency for the

240MHz and 450MHz frequency bands. Figure 5 shows

the corresponding gain vs RF frequency where the gain

curve peaks at a higher frequency compared to the fre-

quency with best match. Note that the overall bandwidth

degrades tuning the matching frequency lower. A similar

technique can be used for 700MHz and 900MHz if gain

flatness is important.

Table 2. LOM Port Input Impedance vs Frequency for EN = High

and PLOM = 0dBm (LOP Terminated with 50Ω AC to Ground)

FREQUENCY

(GHz)

LOM INPUT

IMPEDANCE

REFLECTION COEFFICIENT

MAG

ANGLE

0.2

98-j65

0.499

–29.8

0.25

87-j58

0.462

–34.3

0.3

79-j51

0.421

–38.8

0.4

69-j40

0.354

–45.8

0.5

63-j32

0.296

–52.4

0.6

59-j27

0.256

–58.4

0.7

55-j24

0.225

–64.9

0.8

52-j21

0.203

–72.5

0.9

50-j19

0.188

–79.6

1.0

48-j18

0.18

–86.9

1.2

44-j16

0.178

–101

1.4

41-j15

0.185

–111

1.6

39-j14

0.194

–118

1.8

38-j13

0.2

–123

2.0

37-j12

0.199

–128

2.5

36-j7.8

0.189

–146

3.0

32-j2.4

0.225

–171

3.5

28+j1.0

0.288

176

4.0

25+j2.4

0.35

173

4.5

23+j4.1

0.372

168

5.0

21+j6.2

0.417

162

5.5

19+j7.9

0.472

159

6.0

17+j8.7

0.519

157

Figure 3: Simplified Circuit Schematic

for the LOP and LOM inputs

2.35V

(3.3V IN

SHUTDOWN)

LOM

LOP

VCC1

55881 F03

–

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