PCIMX536AVV8B datasheet(39/180 Pages) FREESCALE

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Electrical Characteristics

i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1

Freescale Semiconductor

4.5.2

LPDDR2 I/O AC Electrical Characteristics

The DDR2/LVDDR2 interface mode fully complies with JESD79-2E DDR2 JEDEC standard release

April, 2008. The DDR3 interface mode fully complies with JESD79-3D DDR3 JEDEC standard release

April, 2008.

Table 21 shows the AC parameters for LPDDR2 I/O operating in DDR2 mode.

Table 22 shows the AC parameters for LPDDR2 I/O operating in LPDDR2 mode.

Table 21. LPDDR2 I/O DDR2 mode AC Characteristics1

1 Note that the JEDEC SSTL_18 specification (JESD8-15a) for class II operation supersedes any specification in this

document.

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

AC input logic high

Vih(ac)

—

Vref+0.25

——

AC input logic low

Vil(ac)

——

—

Vref-0.25

AC differential input voltage2

2 Vid(ac) specifies the input differential voltage |Vtr – Vcp| required for switching, where Vtr is the “true” input signal and Vcp is

the “complementary” input signal. The Minimum value is equal to Vih(ac) – Vil(ac).

Vid(ac)

—

0.5

—

OVDD

Input AC differential cross point voltage3

3 The typical value of Vix(ac) is expected to be about 0.5 * OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)

indicates the voltage at which differential input signal must cross.

Vix(ac)

—

Vref – 0.175

—Vref + 0.175

Output AC differential cross point voltage4

4 The typical value of Vox(ac) is expected to be about 0.5 * OVDD and Vox(ac) is expected to track variation in OVDD. Vox(ac)

indicates the voltage at which differential output signal must cross.

Vox(ac)

—

Vref – 0.125

—Vref + 0.125

Single output slew rate

tsr

At 25

Ω to Vref

0.4

—

V/ns

Skew between pad rise/fall asymmetry +

skew caused by SSN

tSKD

clk=266Mhz

clk=400Mhz

——

0.2

0.1

Table 22. LPDDR2 I/O LPDDR2 mode AC Characteristics1

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

AC input logic high

Vih(ac)

—

Vref + 0.22

—

OVDD

AC input logic low

Vil(ac)

—

Vref – 0.22

AC differential input high voltage2

Vidh(ac)

—

0.44

—

AC differential input low voltage

Vidl(ac)

—

0.44

Input AC differential cross point voltage3

Vix(ac)

Relative to OVDD/2

-0.12

—

0.12

Over/undershoot peak

Vpeak

—

0.35

Over/undershoot area (above OVDD

or below OVSS)

Varea

266MHz

—

0.6

V*ns

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