PCIMX536AVV8B datasheet(46/180 Pages) FREESCALE

46 / 180 page

i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1

Freescale Semiconductor

Electrical Characteristics

NOTE

A potential limitation for minimum clock frequency may exist for some

devices. When the clock frequency is too low, the data bus capturing might

occur after the specified trhoh (RE_B high to output hold) period. Setting the

clock frequency above 25.6 MHz (that is, T = 39 ns) guaranties a proper

operation for devices having trhoh > 15 ns. It is also recommended that the

NFC_FREQ_SEL Fuse be set accordingly to initiate the boot with

33.33 MHz clock.

Lower frequency operation can be supported for most available devices in

the market, relying on data lines Bus-Keeper logic. This depends on device

behavior on the data bus in the time interval between data output valid to

data output high-Z state. In NAND device parameters this period is marked

between trhoh and trhz (RE_B high to output high-Z). In most devices, the

data transition from valid value to high-Z occurs without going through

other states. Setting the data bus pads to Bus-Keeper mode in the IOMUXC

registers, keeps the data bus valid internally after the specified hold time,

allowing proper capturing with slower clock.

Figure 10. Command Latch Cycle Timing

133

33.33

44.333

22.5

2663

1 Boot value NFC_FREQ_SEL Fuse High (burned)

2 Boot value NFC_FREQ_SEL Fuse Low

3 For RBB_MODE=1, using NANDF_RB0 signal for ready/busy indication. This mode require setting the delay line. See the

Reference Manual for details.

Table 33. NFC Clock Settings Examples (continued)

emi_slow_clk (MHz)

nfc_podf (Division Factor)

enfc_clk (MHz)

T-Clock Period (ns)

NFCLE

NFCE_B

NFWE_B

NFIO[7:0]

command

NF9

NF8

NF1

NF2

NF5

NF3

NF4

PCIMX536AVV8B Datasheet(PDF) 46 Page - Freescale Semiconductor, Inc

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