PCIMX536AVV8B datasheet(67/180 Pages) FREESCALE

67 / 180 page

Electrical Characteristics

i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1

Freescale Semiconductor

4.7.2.4

ECSPI Slave Mode Timing

Figure 31 depicts the timing of ECSPI in slave mode. Table 44 lists the ECSPI slave mode timing

characteristics.

4.7.3

Enhanced Serial Audio Interface (ESAI) Timing Parameters

The ESAI consists of independent transmitter and receiver sections, each section with its own clock

generator. Table 45 shows the interface timing values. The number field in the table refers to timing signals

found in Figure 32 and Figure 33.

CS5

SSx Lead Time (CS setup time)

tSCS

5—

CS6

SSx Lag Time (CS hold time)

tHCS

5—

CS7

MOSI Propagation Delay (CLOAD =20pF)

tPDmosi

-0.5

2.5

CS8

MISO Setup Time

tSmiso

8.5

—

CS9

MISO Hold Time

tHmiso

0—

CS10

RDY to SSx Time2

tSDRY

5—

1 See specific I/O AC parameters Section 4.5, “I/O AC Parameters”

2 SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.

Table 44. ECSPI Slave Mode Timing Parameters

Parameter

Symbol

Min

Max

Unit

CS1

SCLK Cycle Time–Read

SCLK Cycle Time–Write

tclk

—ns

CS2

SCLK High or Low Time–Read

SCLK High or Low Time–Write

tSW

—ns

CS4

SSx pulse width

tCSLH

Half SCLK period

—

CS5

SSx Lead Time (CS setup time)

tSCS

5—

CS6

SSx Lag Time (CS hold time)

tHCS

5—

CS7

MOSI Setup Time

tSmosi

4—

CS8

MOSI Hold Time

tHmosi

4—

CS9

MISO Propagation Delay (CLOAD =20pF)

tPDmiso

417

Table 43. ECSPI Master Mode Timing Parameters (continued)

Parameter

Symbol

Min

Max

Unit

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