PCIMX536AVV8B datasheet(77/180 Pages) FREESCALE

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Electrical Characteristics

i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1

Freescale Semiconductor

Figure 39. MII Serial Management Channel Timing Diagram

4.7.5.5

RMII Mode Timing

In RMII mode, FEC_TX_CLK is used as the REF_CLK which is a 50 MHz ±50 ppm continuous reference

clock. FEC_RX_DV is used as the CRS_DV in RMII, and other signals under RMII mode include

FEC_TX_EN, FEC_TXD[1:0], FEC_RXD[1:0] and optional FEC_RX_ER.

The RMII mode timings are shown in Table 52 and Figure 40.

M13

FEC_MDIO (input) to FEC_MDC rising edge hold

—

M14

FEC_MDC pulse width high

60% FEC_MDC period

M15

FEC_MDC pulse width low

60% FEC_MDC period

1 Test conditions: 25pF on each output signal.

Table 52. RMII Signal Timing

No.

Characteristics1

Min

Max

Unit

M16

REF_CLK(FEC_TX_CLK) pulse width high

35%

65%

REF_CLK period

M17

REF_CLK(FEC_TX_CLK) pulse width low

35%

65%

REF_CLK period

M18

REF_CLK to FEC_TXD[1:0], FEC_TX_EN invalid

—

M19

REF_CLK to FEC_TXD[1:0], FEC_TX_EN valid

—

Table 51. MII Transmit Signal Timing (continued)

Characteristics1

Min

Max

Unit

FEC_MDC (output)

FEC_MDIO (output)

M14

M15

M10

M11

M12

M13

FEC_MDIO (input)

PCIMX536AVV8B Datasheet(PDF) 77 Page - Freescale Semiconductor, Inc

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