No. 6266-25/37

LC75804E, LC75804W

The system is reset when the RES pin is set low, and the reset is cleared by setting RES pin high.

2. LC75804E/W internal block states during the reset period

• CLOCK GENERATOR

Reset is applied and the base clock is stopped. However, the OSC pin state (normal or sleep mode) is determined

after the S0 and S1 control data bits are transferred.

• COMMON DRIVER, SEGMENT DRIVER & LATCH

Reset is applied and the display is turned off. However, display data can be input to the latch circuit in this state.

• KEY SCAN

Reset is applied, the circuit is set to the initial state, and at the same time the key scan operation is disabled.

• KEY BUFFER

Reset is applied and all the key data is set to low.

• CCB INTERFACE, CONTROL REGISTER, SHIFT REGISTER

Since serial data transfer is possible, these circuits are not reset.