 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
TUSB1211 Datasheet(PDF) 5 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
TUSB1211 Datasheet(HTML) 5 Page - Texas Instruments |
|
|
5 / 21 page  TUSB1211 www.ti.com SLLSE80 – MARCH 2011 Standalone USB Transceiver Chip Check for Samples: TUSB1211 1 Features • USB2.0 PHY Transceiver Chip, Designed to • Can be Interfaced to Peripheral, Host or OTG Interface With a USB Controller via a ULPI Controller Devices via ULPI. Suited to Portable Interface, Fully Compliant With: Devices or System ASICs with Built-In Controller Core. – Universal Serial Bus Specification Rev. 2.0 • Complete HS-USB Physical Front-End: – On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3 – Supports High Speed (480 Mbit/s), Full Speed (12 Mbit/s) and Low Speed (1.5 Mbit/s) – UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 – Integrated Phase-Locked Loop (PLL) Supporting 2 Clock Frequencies 19.2 MHz/26 – ULPI 12-Pin SDR Interface MHz – USB Battery Charging Specification Rev. 1.1 – Integrated 45 Ω ±10% High-Speed • USB Battery Charger Detection Feature Termination Resistors, 1.5 k Ω Full-Speed – Detection Compliant to USB Charging Device Pullup Resistor, 15 k Ω Host Specification v1.1 Including ACA Detection Termination Resistors – Additional DP Weak Pullup Resistor – Integrated Transmit and Receive Paths for Available for Detection of DP/DM Parallel-to-Serial and Serial-to-Parallel Data Connectivity Conversion • DP/DM Line External Component – USB Data Recovery to Allow Recovery of Compensation (TI Patent Pending) USB Data up to ±500 ppm Frequency Drift • Complete USB OTG Physical Front-End that – Bit-Stuffing Insertion During Transmit and Supports Host Negotiation Protocol (HNP) and Removal During Receive Session Request Protocol (SRP) – Non-Return-to-Zero Inverted (NRZI) • VBUS Overvoltage Protection Circuitry Protects Encoding and Decoding VBUS Pin in Range –2 V to 20 V – Supports Bus Reset, Suspend, Resume and • Internal 5 V Short-Circuit Protection of DP, DM, High-Speed Detection Handshake (Chirp) and ID Pins for Cable Shorting to VBUS Pin – HS USB DP/DM Impedance Programmability • ULPI Interface: for External Component Compensation – I/O Interface (1.8V) Optimized for • OTG Ver1.3: Non-Terminated 50 Ω Line Impedance – Control of External VBUS Switch or Charge – ULPI CLOCK Pin (60 MHz) Supports Both Pump Input and Output Clock Configurations – VBUS Fault Detection – Fully Programmable ULPI-Compliant – Both Session Request Protocol (SRP) Register Set Methods Supported: Data Pulsing and VBUS • Full Industrial Grade Operating Temperature Pulsing Range from –40°C to 85°C – Integrated VBUS Detectors and Cable • Available in a TFBGA36 Ball Package Detection (ID) • USB HS Start-Of-Frame Clock Output Feature • Internal Power-On Reset (POR) Circuit Available on SOF Pin Can be Used to • Flexible System Integration and Very Low Synchronize Another Application, e.g., Audio, Current Consumption, Optimized for Portable With the USB Packet Stream Devices Copyright © 2011, Texas Instruments Incorporated Features 5 |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
