MICRF221 datasheet(10/26 Pages) MICREL

10 / 26 page

Micrel Inc.

MICRF221

October 2008

M9999-100108

(408) 955-1690

Edge

Detector

DOUT

CLK

Data Edge Pulses

Good

Bit

Select 0, 2, 4, 8 Good

Bits Before Wakeup

D15 = 0 for Normal Operation

D15 = 1 for Auto Polled Operation

SQUELCH

Disables DO

SQUELCH Decode

Window

Counter

Decode

Bad Bits

WAKEUP

Timer (300µs)

WATCHDOG

Timer

Serial Control Register

Decode Good

Bit Count

>=7

Good

<=4

Good

Window

Decode

8 Stage

Shift Register

Auto Poll

CLK

D15

CLK

QA1 Bad Bit

Returns to

SLEEP

Figure 4. MICRF221 Autopoll-Bitcheck-Block Diagram

Auto-Polling

The auto-poll block (Figure 4) contains a low power

oscillator to drive the sleep timer when the rest of the

device is powered down, plus circuits to check

whether the received bits are good. Auto-polling is

controlled by bit D15 in the serial register, in

conjunction with bits D12,13,14 to set the sleep timer

period.

Bits D7, D8, are used for control of the

bitchecking operation and bits D9, D10, D11 are used

to adjust the sensitivity of the bitcheck action.

For simple auto-polling without bitchecking, send a

serial command with bit 15 set high and bits D12,

D13, D14 set to the desired sleep time.

The device

will go to sleep for the programmed timer duration

then wake up to receive data if present. Device will

stay awake until serial bit D15 is set low then set high

again to enable a further sleep period. Sleep duty

cycle may be controlled by the timing of serial

commands.

For polling with bitchecking the serial register bits

D7and D8 need to be set for the number of bits to be

checked as good, before the receiver outputs data at

the DO pin.

The bitcheck window bits D9, D10, D11

must also be set to match the data period.

The

default shortest window time gives the least critical

bitcheck action. For better discrimination, the window

setting may be increased up towards the normal

minimum time expected between data edges. Note

that a window time set longer than this will result in all

bits being tested as bad and the device will remain in

sleep polling mode. Now when the serial command is

sent to set bit D15 high the device will go to sleep for

the timer period, then will start to receive and check

bits. The device will output data again at DO as soon

as the programmed number of good RTZ bits have

been received. If a bad bit is seen the device will

return to sleep mode and poll again for good data

after the timeout period. Both high and low periods

are checked for each RTZ bit. If data transitions are

not received the device will return to sleep after the

bitcheck watchdog timeout period unless bit D18 has

been sent, in which case the device will continue to

check bits until sufficient good bits enable the device

to wake up, or bad bits return the device to sleep.

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