PCF2123TS datasheet(19/63 Pages) NXP

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PCF2123

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Product data sheet

Rev. 5 — 27 April 2011

19 of 63

NXP Semiconductors

PCF2123

SPI Real time clock/calendar

The generation of interrupts from the alarm function is controlled via bit AIE (register

Control_2, see Table 7). If bit AIE is enabled, the INT pin follows the condition of bit AF. AF

will remain set until cleared by the interface. Once AF has been cleared, it will only be set

again when the time increments to match the alarm condition once more. Alarm registers

which have their AE_x bit logic 1 are ignored.

Generation of interrupts from the alarm function is described in Section 8.7.3.

Figure 13, Table 22, and Table 23 show an example for clearing bit AF, but leaving bit

MSF and bit TF unaffected. The flags are cleared by a write command, therefore bits 7, 6,

4, 1 and 0 must be written with their previous values. Repeatedly re-writing these bits has

no influence on the functional behavior.

To prevent the timer flags being overwritten while clearing bit AF, logic AND is performed

during a write access. A flag is cleared by writing logic 0 whilst a flag is not cleared by

writing logic 1. Writing logic 1 will result in the flag value remaining unchanged.

Table 23 shows what instruction must be sent to clear bit AF. In this example, bit MSF and

bit TF are unaffected.

Example where only the minute alarm is used and no other interrupts are enabled.

Fig 13. Alarm flag timing

Table 22.

Flag location in register Control_2

Bit

Control_2

--MSF

-AF

Table 23.

Example to clear only AF (bit 3) in register Control_2

Bit

Control_2

001aaf903

minute alarm

minutes counter

INT when AIE = 1

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