These values are internally summed with 16, and thus,

the min and max divider becomes approximately 19

and 28. These limits MUST be followed, to prevent the

delta-sigma number generator from overflowing.

Whenever all of the fhi[11:0] and flo[11:0] are zero, only

an integer divider is used, and the delta-sigma modula-

tor is not in operation. This allows lower current opera-

tion. The 600kHz PLL bandwidth could be used in this

mode to reduce phase noise.

300MHz to 450MHz Frequency-Programmable

ASK/FSK Transmitter

16

______________________________________________________________________________________

BIT

NAME

FUNCTION

0

fload

Effectively changes the PLL frequency to the ones written in registers 2–5. This is a self-reset bit,

and is reset to zero after the operation is completed.

Table 12. Frequency Load Register (Address: 0x06)

BIT

NAME

FUNCTION

0

datain_bit

SPI equivalent of DIN, where the transmitted data can be controlled through the SPI interface. It

should be kept low (0) if only the external DIN pin is used. The external DIN pin should also be kept

low (0) if the SPI datain_bit is used.

Table 13. Data In Register (Address: 0x07)

BIT

NAME

FUNCTION

0

enable_bit

SPI equivalent of ENABLE. It should be kept low (0) if the external ENABLE pin is used. The external

ENABLE pin should also be kept low (0) if the SPI enable_bit is used.

Table 14. Enable Register (Address: 0x08)

BIT

NAME

FUNCTION

2-0

gposel[2:0]

3-bit GPO selector

7-3

RESERVED “0” RESERVED. Set to 0 for normal operation.

Table 15. Configuration 1 Register (Address: 0x09)

DECIMAL

BINARY

GPO

DESCRIPTION

0

000

CKOUT_SDO

Clock/SDO Output. Outputs clock when

CS is high and clock output is enabled;

outputs SDO when

CS is low.

1

001

SDO

SPI Serial Data Output (SDO)

2

010

CKOUT

Clock Output

3

011

RESERVED

RESERVED

4

100

RESERVED

RESERVED

5

101

NoXTAL

Internal Crystal Oscillator Status. High means oscillator is NOT in operation.

6

110

TxREADY

Transmitter Ready Status. High means PLL is locked and MAX7057 is ready to

transmit data.

7

111

datain_bit

A copy of datain_bit

Table 16. General-Purpose Output Selector (gposel[2:0]) for Configuration 1 Register