MC68340 datasheet(5/962 Pages) MOTOROLA

5 / 962 page

Table of Contents

Paragraph

Title

Page

Number

MOTOROLA

MC68360 USER’S MANUAL

Section 1

Introduction

1.1

QUICC Key Features .............................................................................. 1-1

1.2

QUICC Architecture Overview................................................................. 1-4

1.2.1

CPU32+ Core.......................................................................................... 1-5

1.2.2

System Integration Module (SIM60)........................................................ 1-5

1.2.3

Communications Processor Module (CPM) ............................................ 1-6

1.3

Upgrading Designs from the MC68302 ................................................... 1-6

1.3.1

Architectural Approach ............................................................................ 1-6

1.3.2

Hardware Compatibility Issues................................................................ 1-7

1.3.3

Software Compatibility Issues ................................................................. 1-7

1.4

QUICC Glueless System Design............................................................. 1-8

1.5

QUICC Serial Configurations .................................................................. 1-9

1.6

QUICC Serial Configuration Examples ................................................. 1-16

1.7

QUICC System Bus Configurations ...................................................... 1-17

Section 2

Signal Descriptions

2.1

System Bus Signal Index ........................................................................ 2-1

2.1.1

Address Bus ............................................................................................ 2-1

2.1.1.1

Address Bus (A27–A0)............................................................................ 2-1

2.1.1.2

Address Bus (A31–A28).......................................................................... 2-1

2.1.2

Function Codes (FC3–FC0) .................................................................... 2-5

2.1.3

Data Bus.................................................................................................. 2-5

2.1.3.1

Data Bus (D31–D16). .............................................................................. 2-5

2.1.3.2

Data Bus (D15–D0). ................................................................................ 2-6

2.1.4

Parity ....................................................................................................... 2-6

2.1.4.1

Parity (PRTY0). ....................................................................................... 2-6

2.1.4.2

Parity (PRTY1). ....................................................................................... 2-6

2.1.4.3

Parity (PRTY2). ....................................................................................... 2-6

2.1.4.4

Parity (PRTY3). ....................................................................................... 2-6

2.1.5

Memory Controller................................................................................... 2-6

2.1.5.1

Chip Select/Row Address Select (CS6–CS0/RAS6–RAS0) ................... 2-6

2.1.5.2

Chip Select/Row Address Select/Interrupt Acknowledge (CS7/RAS7/IACK7).

2-6

2.1.5.3

Column Address Select/Interrupt Acknowledge (CAS3–CAS0/IACK6, 3, 2,

1).

2-7

2.1.5.4

Address Multiplex (AMUX). ..................................................................... 2-7

2.1.6

Interrupt Request Level (IRQ7–IRQ1)..................................................... 2-7

2.1.7

Bus Control Signals................................................................................. 2-7

2.1.7.1

Data and Size Acknowledge (DSACK1–DSACK0). ................................ 2-8

2.1.7.2

Autovector/Interrupt Acknowledge (AVEC/IACK5).................................. 2-8

2.1.7.3

Address Strobe (AS). .............................................................................. 2-8

2.1.7.4

Data Strobe (DS)..................................................................................... 2-8

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