AD9837 datasheet(13/28 Pages) AD

13 / 28 page

AD9837

Rev. 0 | Page 13 of 28

FUNCTIONAL DESCRIPTION

SERIAL INTERFACE

The AD9837 has a standard 3-wire serial interface that is

compatible with the SPI, QSPI™, MICROWIRE®, and DSP

interface standards.

Data is loaded into the device as a 16-bit word under the control

of a serial clock input, SCLK. The timing diagram for this oper-

ation is given in Figure 3.

FSYNC is a level triggered input that acts as a frame synchroni-

zation and chip enable input. Data can be transferred into the

device only when FSYNC is low. To start the serial data transfer,

FSYNC should be taken low, observing the minimum FSYNC

to SCLK falling edge setup time, t7 (see Table 2). After FSYNC

goes low, serial data is shifted into the input shift register of the

device on the falling edges of SCLK for 16 clock pulses. FSYNC

can be taken high after the 16th falling edge of SCLK, observing

the minimum SCLK falling edge to FSYNC rising edge time, t8.

Alternatively, FSYNC can be kept low for a multiple of 16 SCLK

pulses and then brought high at the end of the data transfer. In

this way, a continuous stream of 16-bit words can be loaded

while FSYNC is held low; FSYNC goes high only after the 16th

SCLK falling edge of the last word loaded.

The SCLK can be continuous, or it can idle high or low between

write operations. In either case, it must be high when FSYNC

goes low (t11).

For an example of how to program the AD9837, see the AN-1070

Application Note on the Analog Devices, Inc., website. The

AD9837 has the same register settings as the AD9833/AD9834.

LATENCY PERIOD

A latency period is associated with each asynchronous write

operation in the AD9837. If a selected frequency or phase

or eight MCLK cycles before the analog output changes. The

delay can be seven or eight cycles, depending on the position

of the MCLK rising edge when the data is loaded into the

destination register.

CONTROL REGISTER

The AD9837 contains a 16-bit control register that allows the

user to configure the operation of the AD9837. All control bits

other than the MODE bit are sampled on the internal falling

edge of MCLK.

Figure 20 illustrates the functions of the control bits. Table 7

describes the individual bits of the control register. The different

functions and the various output options of the AD9837 are

described in more detail in the following sections.

To inform the AD9837 that the contents of the control register

will be altered, Bit D15 and Bit D14 must be set to 0, as shown

in Table 6.

Table 6. Control Register Bits

D15

D14

D13 to D0

Control bits

SIN

ROM

PHASE

ACCUMULATOR

(28-BIT)

SLEEP12

SLEEP1

RESET

MODE + OPBITEN

DIV2

OPBITEN

(LOW POWER)

10-BIT DAC

MUX

VOUT

MUX

DIGITAL

OUTPUT

(ENABLE)

DIVIDE

BY 2

D15

D14

D13

B28

D12

HLB

D11

FSEL

D10

PSEL

RESET

SLEEP1

SLEEP12

OPBITEN

DIV2

MODE

Figure 20. Function of Control Bits

AD9837 Datasheet(PDF) 13 Page - Analog Devices

AD9837 Datasheet(HTML) 13 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL