AD9837 datasheet(3/28 Pages) AD

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AD9837

Rev. 0 | Page 3 of 28

SPECIFICATIONS

VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, TA = TMIN to TMAX, unless otherwise noted.

Table 1.

Parameter1

Min

Typ

Max

Unit

Test Conditions/Comments

SIGNAL DAC SPECIFICATIONS

Resolution

Bits

Update Rate

A Grade

MSPS

B Grade

MSPS

VOUT Maximum

0.645

VOUT Minimum

Vp-p

0.610

VOUT TC

200

ppm/°C

DC Accuracy

Integral Nonlinearity (INL)

±1.0

LSB

Differential Nonlinearity (DNL)

±0.5

LSB

DDS SPECIFICATIONS

Dynamic Specifications

Signal-to-Noise Ratio (SNR)

A Grade

−64

fMCLK = 5 MHz, fOUT = fMCLK/4096

B Grade

−64

fMCLK = 16 MHz, fOUT = fMCLK/4096

Total Harmonic Distortion (THD)

A Grade

−68

dBc

fMCLK = 5 MHz, fOUT = fMCLK/4096

B Grade

−68

dBc

fMCLK = 16 MHz, fOUT = fMCLK/4096

Spurious-Free Dynamic Range (SFDR)

Wideband (0 to Nyquist)

A Grade

−65

dBc

fMCLK = 5 MHz, fOUT = fMCLK/50

B Grade

−65

dBc

fMCLK = 16 MHz, fOUT = fMCLK/50

Narrow-Band (±200 kHz)

A Grade

−94

dBc

fMCLK = 5 MHz, fOUT = fMCLK/50

B Grade

−97

dBc

fMCLK = 16 MHz, fOUT = fMCLK/50

Clock Feedthrough

−67

dBc

Wake-Up Time

LOGIC INPUTS

Input High Voltage, VINH

1.7

2.3 V to 2.7 V power supply

2.0

2.7 V to 3.6 V power supply

2.8

4.5 V to 5.5 V power supply

Input Low Voltage, VINL

0.5

2.3 V to 2.7 V power supply

0.7

2.7 V to 3.6 V power supply

0.8

4.5 V to 5.5 V power supply

Input Current, IINH/IINL

Input Capacitance, CIN

POWER SUPPLIES

fMCLK = 16 MHz, fOUT = fMCLK/4096

VDD

2.3

5.5

IDD

A Grade

3.7

5.0

IDD code dependent; see Figure 6

B Grade

4.5

5.5

IDD code dependent; see Figure 7

Low Power Sleep Mode

0.5

0.8

DAC powered down (SLEEP1 and

SLEEP12 bits = 11; see Table 15)

1 Operating temperature range is −40°C to +125°C; typical specifications are at 25°C.

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