ADP2126/ADP2127

Rev. A | Page 6 of 20

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

MODE VIN

SW

FB

GND

1

A

B

C

2

BALL A1

INDICATOR

EXTCLK

TOP VIEW

BALL/PAD SIDE DOWN

BUMPS/PADS ON OPPOSITE SIDE

(Not to Scale)

Figure 5. Pin Configuration

Pin No.

Mnemonic

Description

A1

MODE

Mode Select. This pin toggles between auto mode (PFM and PWM switching) and PWM mode. Set MODE low to

allow the part to operate in auto mode. Pull MODE high to force the part to operate in PWM mode. The voltage

applied to MODE should never be higher than the voltage applied to VIN. Do not leave this pin floating.

A2

VIN

Power Supply Input.

B1

SW

Switch Node.

B2

EXTCLK

External Clock Enable Signal. The ADP2126/ADP2127 power up when a clock signal (6 MHz to 27 MHz) or a logic high

signal (EXTCLK ≥ 1.3 V) is detected on this pin. (The logic high enable feature is only available on certain models.)

C1

FB

Feedback Divider Input. Connect the output capacitor from FB to GND to set the output voltage ripple and to

complete the control loop.

C2

GND

Ground.