ACS103 Issue 2.03 May 1996.

7

2

Figure 4. 6 Full-duplex channels in data transmission mode

TxD1

RxD1

TxD2

RxD2

TxD3

RxD3

XI3

XO3

RxD1

TXD1

RxD2

XI3

XO3

DSR / XO2

DTR / XI2

RxD3

TxD3

TxD2

DTR / XI2

DSR / XO2

DTE

ACS103

ACS103

DCE

90 %

90 %

10 %

10 %

t

r

t

f

TxCL and RxCL clock pulse widths

t

wl

t

wh

t

sut

t

ht

t

sur

t

hr

TxD

RxD

TxCL

RxCL

Transmit set-up and hold times

Receive set-up and hold times

Digital Outputs rise and fall times

Figure 2. Timing diagrams

Figure 3. Recommended power supply layout

Single Fiber Link

RTS / XI1

CTS / XO1

CTS / XO1

RTS / XI1

VD+ pins are 13, 37, 38, 67 and 68.

GND pins are 23, 35, 36, 47, 65 and 66.

All capacitors must be placed

very close to the ACS103.

VA+

VD+

VG

GND

GND

Pin 49 and Pin 54

should be connected together

GND

CON1

CON2

ACS103

CNT

100 nF

47µF

100 nF

100 nF

22 - 33 nF

47 µH

+5V

47 µH

GND

V+