TMS320F2812 datasheet(28/170 Pages) TI

28 / 170 page

Block

Start Address

0x00 0000

M0 Vector - RAM (32 x 32)

(Enabled if VMAP = 0)

BROM Vector - ROM (32 x 32)

(Enabled if VMAP = 1, MP/

= 0, ENPIE = 0)

XINTF Vector - RAM (32 x 32)

(Enabled if VMAP = 1, MP/

= 1, ENPIE = 0)

Data Space

Prog Space

M0 SARAM (1K x 16)

M1 SARAM (1K x 16)

Peripheral Frame 0

0x00 0040

0x00 0400

0x00 0800

PIE Vector - RAM

(256 x 16)

(Enabled if

VMAP = 1, ENPIE = 1)

L0 SARAM (4K x 16, Secure Block)

Peripheral Frame 1

(Protected)

Peripheral Frame 2

(Protected)

L1 SARAM (4K x 16, Secure Block)

OTP (or ROM) (1K x 16, Secure Block)

Flash (or ROM) (128K x 16, Secure Block)

128-Bit Password

H0 SARAM (8K x 16)

Boot ROM (4K x 16)

(Enabled if MP/

= 0)

0x00 0D00

0x00 0E00

0x00 2000

0x00 6000

0x00 7000

0x00 8000

0x00 9000

0x00 A000

0x3D 7800

0x3D 7C00

0x3F 7FF8

0x3F 8000

0x3F A000

0x3F F000

0x3F FFC0

Data Space

Prog Space

XINTF Zone 0 (8K x 16,

)

XZCS0AND1

XINTF Zone 1 (8K x 16,

) (Protected)

XZCS0AND1

XINTF Zone 2 (0.5M x 16,

)

XZCS2

XINTF Zone 6 (0.5M x 16,

)

XZCS6AND7

XINTF Zone 7 (16K x 16,

)

(Enabled if MP/

= 1)

XZCS6AND7

On-Chip Memory

External Memory XINTF

Only one of these vector maps - M0 vector, PIE vector, BROM vector, XINTF vector - should be enabled at a time.

LEGEND:

0x08 0000

0x00 4000

0x10 0000

0x18 0000

0x3F C000

0x00 2000

0x3D 8000

Reserved

Reserved (1K)

Reserved

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S – APRIL 2001 – REVISED MARCH 2011

www.ti.com

3.1

Memory Map

Memory blocks are not to scale.

Reserved locations are reserved for future expansion. Application should not access these areas.

Boot ROM and Zone 7 memory maps are active either in on-chip or XINTF zone depending on MP/MC, not in both.

Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.

User program cannot access these memory maps in program space.

“Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.

Certain memory ranges are EALLOW protected against spurious writes after configuration.

Zones 0 and 1 and Zones 6 and 7 share the same chip select; hence, these memory blocks have mirrored locations.

Figure 3-2. F2812/C2812 Memory Map

Functional Overview

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Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2812 Datasheet(PDF) 28 Page - Texas Instruments

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