ICS1532 datasheet(12/36 Pages) IDT

12 / 36 page

110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR

ICS1532

MDS 1532 G

Revision 060804

www.idt.com

4.4

Complete Register Set

Table 4-2.

New Register Set Outline

Index

Access

Bit #

Bit Name

Brief Description

Reset

Value

00h

Input Control

R/W

7-6 HSYNC_Sel

Select HSYNC Input Threshold for Main PLL

– See Chapter 11-3, “Pin Specific I/O AC

Parameters”

In_Sel

Select Main PLL Phase Detector Input

– 0 = HSYNC source selected by Reg0:7-6

– 1 = Input is the OSC pin

Fdbk Div Load

Select load for Feedback Divider

– 0 = New values loaded on a pixel PLL

reset.-(Normal Operation)

– 1 = New values loaded on the HSYNC without a

PLL reset - Only usable for small changes

Fdbk_Pol

Select feedback polarity for Phase/Frequency Detector

– 0 = Main/Pixel PLL uses the rising edge

– 1 = Main/Pixel PLL uses the falling edge

Ref_Pol

Select polarity of external reference

– 0 = Rising HSYNC Edge Selected

– 1 = Falling HSYNC Edge Selected

CP_Pol

Select polarity of COAST Input if Reg0:0=1

– 0 = Charge Pump enabled if COAST pin high

– 1 = Charge Pump enabled if COAST pin low

CP_En

Charge Pump (CP) Enable

– 0 = CP enabled by Reg0:1 and COAST

– 1 = CP always Enabled - Normal Operation

01h

Loop Control

R/W. D-PLL.

7-6 Reserved

Reserved

5-4 VCOS

Select VCO Scaler Value

VCO frequency = (Output frequency) * VCOS(d)

– 00 = 2:1

– 01 = 4:1

– 10 = 8:1

– 11 = 16:1

Reserved

2-0 ICP

ICP - Charge Pump Current

– 000 = ~2

μA

– 001 = ~4

μA

– 010 = ~8

μA (Typical with Internal Filter)

– 011 = ~16

μA.

– 100 = ~32

μA

– 101 = ~64

μA

– 110 = ~120

μA.

– 111 = ~190

μA

02h

Fdbk Div 0

R/W. D-PLL.

7-0 FDBK [7-0]

Feedback Divider LSB’s bits 7-0 - See Reg3 for MSB’s

– Controls the number of CLK outputs per HSYNC

– Actual # of CLK’s = 8 + (Reg3 + Reg2)d

N/A

03h

Fdbk Div 1

R/W. D-PLL.

7-4 Reserved

Reserved

–

3-0 FDBK [11-8]

Feedback Divider MSB’s bits 11-8 - See Reg2

N/A

04h

DPA Offset

R/W

7-6 Reserved

Reserved

5-0 DPA_OS

Dynamic Phase Adjust (DPA) Offset

– See Chapter 5, “DPA Operation”

The value programmed here must be less than the

DPA Resolution controlled by Reg5:1-0

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