GS9062 datasheet(35/46 Pages) GENNUM

35 / 46 page

GS9062 Data Sheet

22209 - 7

February 2007

35 of 46

3.8 Serial Digital Data PLL

To obtain a clean clock signal for serialization and transmission, the input PCLK is

locked to an external reference signal via the GS9062's integrated phase-locked

loop. This PLL is also responsible for generating all internal clock signals required

by the device.

Internal division ratios for the locked PCLK are determined by the setting of the

20bit/10bit pin as shown in Table 3-10.

3.8.1 External VCO

The GS9062 requires the GO1555/GO1525* external voltage controlled oscillator

as part of its internal PLL.

Power for the external VCO is generated entirely by the GS9062 from an integrated

voltage regulator. The internal regulator uses +3.3V supplied on the CP_VDD /

CP_GND pins to provide +2.5V on the VCO_VCC / VCO_GND pins.

The external VCO produces a reference signal for the PLL, input on the VCO pin

of the device. Both reference and control signals should be referenced to the

supplied VCO_GND as shown in the recommended application circuit of Typical

Application Circuit on page 42.

*For new designs use GO1555

3.8.2 Lock Detect Output

The lock detect block controls the serial digital output signal and indicates to the

application layer the lock status of the device via the LOCKED output pin.

LOCKED will be asserted HIGH if and only if the internal data PLL has locked the

PCLK signal to the external VCO reference signal and one of the following is true:

1. The device is set to operate in SMPTE mode and has detected SMPTE TRS

words in the serial stream; or

2. The device is set to operate in DVB-ASI mode and has detected K28.5 sync

characters in the serial stream; or

3. The device is set to operate in Data-Through mode.

Table 3-10: Serial Digital Output Rates

20bit/10bit

Supplied PCLK Rate

Serial Digital

Output Rate

HIGH

13.5MHz

270Mb/s

LOW

27MHz

270Mb/s

GS9062 Datasheet(PDF) 35 Page - Gennum Corporation

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