6

Atmel LED Driver-MSLB9061

PARAMETER

CONDITIONS AND NOTES

MIN

TYP

MAX

UNIT

I²C SWITCHING CHARACTERISTICS

SCL clock frequency

1000

kHz

Bus timeout

25

ms

Bus free time between a STOP and START

condition

0.5

µs

Hold time for a repeated START condition

0.26

µs

Set-up time for a repeated START condition

0.26

µs

Set-up time for STOP condition

0.26

µs

Data hold time

10

ns

Data valid acknowledge time

(Note 3)

0.05

0.45

µs

Data valid time

(Note 4)

0.05

0.45

µs

Data set-up time

100

ns

LOW period of the SCL clock

0.5

µs

HIGH period of the SCL clock

0.26

µs

Fall time of SDA and SCL signals

(Note 5,6)

120

ns

Rise time of both SDA and SCL signals

120

ns

Pulse width of spikes that must be

suppressed by the input filter

(Note 7)

50

ns

SDA, SCL, AD0 input capacitance

10

pF

Note 1. Full power available with PWR input voltage greater than 6.5V. For 3.1V to 3.6V operation, doubling charge pump(U2)

and C12, C13 are required.

Note 2. Minimum SCL clock frequency is limited by the bus timeout feature, which resets the serial bus interface if either SDA or SCL

is held low for 25ms. Disable bus timeout feature for DC operation.

Note 3. Time for acknowledge signal from SCL low to SDA (out) low.

Note 4. Minimum time for SDA data out to be valid following SCL low.

Note 5. A master device must internally provide a hold time of at least 300ns for the SDA signal (refer to the V

in order to bridge the undefined region of SCL falling edge.

Note 6. The maximum fall times for the SDA and SCL bus lines are specified at 300ns. The maximum fall time for the SDA output

stage is specified at 250ns. This allows series protection resistors to be connected between SDA and SCL and the

SDA/SCL bus lines without exceeding the maximum specified tall time.

Note 7. Input filters on the SDA, SCL, and AD0 inputs suppress noise less than 50ns.