HT67F60 datasheet(125/242 Pages) HOLTEK

125 / 242 page

HT67F30/HT67F40/HT67F50/HT67F60

TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM

Rev. 1.50

124

March 06 , 2012

Rev. 1.50

125

March 06 , 2012

16-bit STM, PWM Mode, Edge-aligned Mode, T0DPX=0

CCRP

1~255

000b

Period

CCRP x 256

65536

Duty

CCRA

If fSYS = 16MHz, TM clock source select fSYS/4, CCRP = 2 and CCRA = 128,

The STM PWM output frequency = (fSYS/4) / (2 x 256) = fSYS/2048 = 7.8125kHz, duty = 128 / (2 x

256) = 25%.

If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the

PWM output duty is 100%.

16-bit STM, PWM Mode, Edge-aligned Mode, T0DPX=1

CCRP

1~255

000b

Period

CCRA

Duty

CCRP x 256

65536

The PWM output period is determined by the CCRA register value together with the TM clock

while the PWM duty cycle is defined by the (CCRP x 256) except when the CCRP value is equal to

000b.

Counter Value

0x3FF

CCRP

CCRA

TnON

TnPAU

TnPOL

CCRP Int.

Flag TnPF

CCRA Int.

Flag TnAF

TM O/P Pin

Time

CCRP=0

CCRP > 0

Counter overflow

CCRP > 0

Counter cleared by CCRP value

Pause

Resume

Stop

Counter

Restart

TnCCLR = 0; TnM [1:0] = 00

Output pin set to

initial Level Low

if TnOC=0

Output Toggle with

TnAF flag

Note TnIO [1:0] = 10

Active High Output select

Here TnIO [1:0] = 11

Toggle Output select

Output not affected by TnAF

flag. Remains High until reset

by TnON bit

Output Pin

Reset to Initial value

Output controlled by

other pin-shared function

Output Inverts

when TnPOL is high

Compare Match Output Mode — TnCCLR = 0

Note: 1. With TnCCLR=0 a Comparator P match will clear the counter

2. The TM output pin is controlled only by the TnAF flag

3. The output pin is reset to itsinitial state by a TnON bit rising edge

HT67F60 Datasheet(PDF) 125 Page - Holtek Semiconductor Inc

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