HT67F60 datasheet(144/242 Pages) HOLTEK

144 / 242 page

Rev. 1.50

144

March 06 , 2012

Rev. 1.50

145

March 06 , 2012

HT67F30/HT67F40/HT67F50/HT67F60

TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPRO

Single Pulse Mode

To select this mode, the required bit pairs, TnAM1, TnAM0 and TnBM1, TnBM0 should be set to

10 respectively and also the corresponding TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits should be

set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single

shot pulse on the TM output pin.

The trigger for the pulse TPnA output leading edge is a low to high transition of the TnON bit,

which can be implemented using the application program. The trigger for the pulse TPnB output

leading edge is a compare match from Comparator B, which can be implemented using the

application program. However in the Single Pulse Mode, the TnON bit can also be made to

automatically change from low to high using the external TCKn pin, which will in turn initiate the

Single Pulse output of TPnA. When the TnON bit transitions to a high level, the counter will start

running and the pulse leading edge of TPnA will be generated. The TnON bit should remain high

when the pulse is in its active state. The generated pulse trailing edge of TPnA and TPnB will be

generated when the TnON bit is cleared to zero, which can be implemented using the application

program or when a compare match occurs from Comparator A.

However a compare match from Comparator A will also automatically clear the TnON bit and thus

generate the Single Pulse output trailing edge of TPnA and TPnB. In this way the CCRA value can

be used to control the pulse width of TPnA. The CCRA-CCRB value can be used to control the

pulse width of TPnB. A compare match from Comparator A and Comparator B will also generate

TM interrupts. The counter can only be reset back to zero when the TnON bit changes from low to

high when the counter restarts. In the Single Pulse Mode CCRP is not used. The TnCCLR bit is also

not used.

TnON bit

0  1

S/W Command

SET“TnON”

TCKn Pin

Transition

CCRB

Leading Edge

TnON bit

1  0

CCRA

Trailing Edge

S/W Command

CLR“TnON”

CCRA Compare

Match

TPnA Output Pin

TPnB Output Pin

Pulse Width = (CCRA-CCRB) Value

Pulse Width = CCRA Value

Counter Value

CCRB

CCRA

Time

TnON = 1

CCRB Compare

Match

TnON bit

1  0

S/W Command

CLR“TnON”

CCRA Compare

Match

CCRB

Trailing Edge

CCRA

Leading Edge

Single Pulse Generation

HT67F60 Datasheet(PDF) 144 Page - Holtek Semiconductor Inc

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