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HT67F60 Datasheet(PDF) 227 Page - Holtek Semiconductor Inc

Part # HT67F60
Description  TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM
PDF  242 Pages
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Manufacturer  HOLTEK [Holtek Semiconductor Inc]
Direct Link  http://www.holtek.com
Logo HOLTEK - Holtek Semiconductor Inc

HT67F60 Datasheet(HTML) 227 Page - Holtek Semiconductor Inc

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HT67F30/HT67F40/HT67F50/HT67F60
TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM
Rev. 1.50
226
March 06 , 2012
Rev. 1.50
227
March 06 , 2012
Mnemonic
Description
Cycles
Flag Affected
Data Move
MOV A,[m]
Move Data Memory to ACC
1
None
MOV [m],A
Move ACC to Data Memory
1Note
None
MOV A,x
Move immediate data to ACC
1
None
Bit Operation
CLR [m].i
Clear bit of Data Memory
1Note
None
SET [m].i
Set bit of Data Memory
1Note
None
Branch
JMP addr
Jump unconditionally
2
None
SZ [m]
Skip if Data Memory is zero
1Note
None
SZA [m]
Skip if Data Memory is zero with data movement to ACC
1Note
None
SZ [m].i
Skip if bit i of Data Memory is zero
1Note
None
SNZ [m].i
Skip if bit i of Data Memory is not zero
1Note
None
SIZ [m]
Skip if increment Data Memory is zero
1Note
None
SDZ [m]
Skip if decrement Data Memory is zero
1Note
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
1Note
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
1Note
None
CALL addr
Subroutine call
2
None
RET
Return from subroutine
2
None
RET A,x
Return from subroutine and load immediate data to ACC
2
None
RETI
Return from interrupt
2
None
Table Read
TABRDC [m]
Read table (current page) to TBLH and Data Memory
2Note
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
2Note
None
Miscellaneous
NOP
No operation
1
None
CLR [m]
Clear Data Memory
1Note
None
SET [m]
Set Data Memory
1Note
None
CLR WDT
Clear Watchdog Timer
1
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
1
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
1
TO, PDF
SWAP [m]
Swap nibbles of Data Memory
1Note
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
1
None
HALT
Enter power down mode
1
TO, PDF
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the "CLR WDT1" and "CLR WDT2" instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both "CLR WDT1" and "CLR
WDT2" instructions are consecutively executed. Otherwise the TO and PDF flags remain
unchanged.



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