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RL78 Datasheet(PDF) 67 Page - Renesas Technology Corp

Part # RL78
Description  True Low Power Platform (as low as 66 ?쵡/MHz, and 0.60 ?쵡 for RTC LVD), 1.6 V to 5.5 V operation
PDF  100 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

RL78 Datasheet(HTML) 67 Page - Renesas Technology Corp

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RL78/G14
2. ELECTRICAL SPECIFICATIONS
R01DS0053EJ0100 Rev. 1.00
Page 67 of 97
Feb 21, 2012
Caution
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
Caution
Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remark
p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM number (g = 3, 5)
CSI mode connection diagram (during communication at same potential)
CSI mode connection diagram (during communication at same potential)
(Slave Transmission of slave select input function (CSI00))
Remark 1.
p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31)
Remark 2.
m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)
(4)
During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = -40 to +85
C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
(2/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SSI00 setup time
tSSIK
DAPmn = 0
2.7 V
 EVDD0  5.5 V
120
ns
1.8 V
 EVDD0 < 2.7 V
200
ns
1.6 V
 EVDD0 < 1.8 V
400
ns
DAPmn = 1
2.7 V
 EVDD0  5.5 V
1/fMCK + 120
ns
1.8 V
 EVDD0 < 2.7 V
1/fMCK + 200
ns
1.6 V
 EVDD0 < 1.8 V
1/fMCK + 400
ns
SSI00 hold time
tKSSI
DAPmn = 0
2.7 V
 EVDD0  5.5 V
1/fMCK + 120
ns
1.8 V
 EVDD0 < 2.7 V
1/fMCK + 200
ns
1.6 V
 EVDD0 < 1.8 V
1/fMCK + 400
ns
DAPmn = 1
2.7 V
 EVDD0  5.5 V
120
ns
1.8 V
 EVDD0 < 2.7 V
200
ns
1.6 V
 EVDD0 < 1.8 V
400
ns
SCKp
SOp
User's device
SCK
SI
SIp
SO
RL78/G14
SCK00
SO00
User's device
SCK
SI
SI00
SO
SSI00
SS0
RL78/G14



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